AD7457_05 datasheet(5/20 Pages) AD

部品番号	AD7457

部品情報	Low Power, Pseudo Differential, 100 kSPS

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AD7457

Rev. A | Page 5 of 20

TIMING SPECIFICATIONS1

VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK2

10

kHz min

10

MHz max

tCONVERT

16 × tSCLK

tSCLK = 1/fSCLK

1.6

µs max

t2

10

ns min

CS rising edge to SCLK falling edge setup time

t33

20

ns max

Delay from CS rising edge until SDATA three-state disabled

t43

40

ns max

Data access time after SCLK falling edge

t5

0.4 tSCLK

ns min

SCLK high pulse width

t6

0.4 tSCLK

ns min

SCLK low pulse width

t7

10

ns min

SCLK edge to data valid hold time

t84

10

ns min

SCLK falling edge to SDATA three-state enabled

35

ns max

SCLK falling edge to SDATA three-state enabled

tPOWER-UP5

1

µs max

Power-up time from full power-down

tPOWER-DOWN

7.4

µs min

Minimum time spent in power-down

1 The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of

1.6 V. See

and the Serial

section.

Figure 2

Interface

2 Mark/space ratio for the SCLK input is 40/60 to 60/40.

3 Measured with the load circuit of

and defined as the time required for the output to cross 0.8 V or 2.4 V with V

Figure 3

Figure 3.

DD

= 5 V, and the time required for the output to

cross 0.4 V or 2.0 V for VDD = 3 V.

4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of

The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

5 See the

section.

Power Consumption

0

DB11 DB10

DB2

DB1

DB0

0

t4

t6

t7

t8

t3

TPOWERDOWN

THREE-STATE

AUTOMATIC

POWER DOWN

TPOWERUP

TACQUISITION

POWER

UP

CONVERT

START

TRACK

TACQUISTION

TPOWERUP

4 LEADING ZEROS

SDATA

SCLK

CS

THREE-STATE

t2

t5

HOLD

Figure 2. AD7457 Serial Interface Timing Diagram

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同様の説明 - AD7457_05

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