74AC11873

DUAL 4BIT DTYPE LATCH

WITH 3STATE OUTPUTS

SCAS095 − JANUARY 1990 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Copyright

2−1

Lines Directly

PCB Layout

Minimize High-Speed Switching Noise

CMOS) 1-

µm Process

at 125

°C

description

This dual 4-bit transparent D-type latch features

3-state outputs designed specifically for bus

driving. This makes these devices particularly

suitable for implementing buffer registers, I/O

ports, bidirectional bus drivers, and working

registers.

When the latch-enable (1LE or 2LE) input is high, the Q outputs will follow the data (D) inputs in true form,

according to the function table. When LE is taken low, the outputs will be latched. When the clear (1CLR or

2CLR) input goes low, the Q outputs go low independently of LE. The outputs are in a high-impedance state

when the output-control (1OC or 2OC) input is at a high logic level.

The 74AC11873 is characterized for operation from − 40

°C to 85°C.

FUNCTION TABLE

(each 4-bit latch)

INPUTS

OUTPUT

OC

CLR

LE

D

OUTPUT

Q

L

L

X

X

L

L

HH

H

H

L

HH

L

L

L

HL

X

Q0

H

X

X

X

Z

DW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1LE

1Q1

1Q2

1Q3

1Q4

GND

GND

GND

GND

2Q1

2Q2

2Q3

2Q4

2LE

1OC

1CLR

1D1

1D2

1D3

1D4

2D1

2D2

2D3

2D4

2CLR

2OC

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.