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74ACT11821DWR データシート(PDF) 1 Page - Texas Instruments

部品番号 74ACT11821DWR
部品情報  10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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74ACT11821DWR データシート(HTML) 1 Page - Texas Instruments

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54ACT11821, 74ACT11821
10BIT BUSINTERFACE FLIPFLOPS
WITH 3STATE OUTPUTS
SCAS156A − NOVEMBER 1990 − REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
Copyright
1993, Texas Instruments Incorporated
2−1
Inputs Are TTL-Voltage Compatible
Provides Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-
µm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Ceramic 300-mil
DIPs
description
These 10-bit flip-flops feature 3-state outputs
designed specifically for driving highly-capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
On the positive transition of the clock the Q outputs
will follow the D inputs.
A buffered output enable (OE) input can be used
to place the ten outputs in either a normal logic
state (high or low level) or a high-impedance state.
In the high-impedance state the outputs neither
load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components.
The output enable (OE)does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The 54ACT11821 is characterized for operation over the full military temperature range of −55
°C to 125°C. The
74ACT11821 is characterized for operation form − 40
°C to 85°C.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
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1Q
2Q
3Q
4Q
5Q
GND
GND
GND
GND
6Q
7Q
8Q
9Q
10Q
OE
1D
2D
3D
4D
5D
VCC
VCC
6D
7D
8D
9D
10D
CLK
54ACT11821 . . . JT PACKAGE
74ACT11821 . . . DW PACKAGE
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8D
9D
10
CLK
10Q
9Q
8Q
2D
1D
OE
1Q
2Q
3Q
4Q
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54ACT11821 . . . FK PACKAGE
(TOP VIEW)
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(TOP VIEW)


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