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DAC5674IPHP データシート(PDF) 7 Page - Texas Instruments |
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DAC5674IPHP データシート(HTML) 7 Page - Texas Instruments |
7 / 39 page DAC5674 SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005 www.ti.com 7 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AGND 37, 41, 44 I Analog ground return AVDD 45, 46 I Analog supply voltage BIASJ 40 O Full-scale output current bias CLK 29 I External clock input CLKC 30 I Complementary external clock input CLKGND 31 I Ground return for internal clock buffer CLKVDD 32 I Internal clock buffer supply voltage D[13..0] 3−16 I Data bits 0 through 13 D13 is most significant data bit (MSB) D0 is least significant data bit (MSB) DIV[1..0] 27,28 I PLL prescaler divide ratio settings DGND 1, 2, 19, 24 I Digital ground return DVDD 21, 47, 48 I Digital supply voltage EXTIO 39 I/O Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). Used as internal reference output when EXTLO = AGND, requires a 0.1- µF decoupling capacitor to AGND when used as reference output EXTLO 38 I For internal reference connect to AGND. Connect to AVDD to disable the internal reference HP1 17 I Filter 1 high-pass setting. Active high HP2 18 I Filter 2 high-pass setting. Active high IOGND 20 I Input digital ground return IODVDD 22 I Input digital supply voltage IOUT1 43 O DAC current output. Full scale when all input bits are set 1 IOUT2 42 O DAC complementary current output. Full scale when all input bits are 0 LPF 35 I PLL loop filter connection PLLGND 33 I Ground return for internal PLL PLLLOCK 25 O PLL lock status bit. PLL is locked to input clock when high. Provides output clock equal to the data rate when the PLL is disabled. PLLVDD 34 I Internal PLL supply voltage. Connect to PLLGND to disable PLL clock multiplier. RESET 26 I Reset internal registers. Active high SLEEP 36 I Asynchronous hardware power-down input. Active high. Internally pull down. X4 23 I 4 × interpolation mode. Active high. Filter 1 is bypassed when connected to DGND |
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同様の説明 - DAC5674IPHP |
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