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74FCT2574ATSOCTE4 データシート(PDF) 1 Page - Texas Instruments

部品番号 74FCT2574ATSOCTE4
部品情報  8-BIT REGISTER WITH 3-STATE OUTPUTS
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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74FCT2574ATSOCTE4 データシート(HTML) 1 Page - Texas Instruments

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CY74FCT2574T
8-BIT REGISTER
WITH 3-STATE OUTPUTS
SCCS076 – OCTOBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Function and Pinout Compatible With FCT
and F Logic
D 25-Ω Output Series Resistors to Reduce
Transmission-Line Reflection Noise
D Reduced VOH (Typically = 3.3 V) Version of
Equivalent FCT Functions
D Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
D Ioff Supports Partial-Power-Down Mode
Operation
D Matched Rise and Fall Times
D Fully Compatible With TTL Input and
Output Logic Levels
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D 3-State Outputs
D 12-mA Output Sink Current
15-mA Output Source Current
D Edge-Triggered D-Type Inputs
D 250-MHz Typical Switching Rate
description
The CY74FCT2574T is a high-speed, low-power, octal D-type flip-flop featuring separate D-type inputs for each
flip-flop. On-chip termination resistors at the outputs reduce system noise caused by reflections. The
CY74FCT2574T can replace the CY74FCT574T to reduce noise in an existing design. This device has 3-state
outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE) inputs are common to all
flip-flops. The CY74FCT2574T is identical to the CY74FCT2374T, except that on the CY74FCT2574T all
outputs are on one side of the package and all inputs are on the other side. The flip-flops in the CY74FCT2574T
store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high
CP transition. When OE is low, the contents of the flip-flops are available at the outputs. When OE is high, the
outputs are in the high-impedance state. The state of OE does not affect the state of the flip-flops.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Copyright
 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
VCC
O0
O1
O2
O3
O4
O5
O6
O7
CP
Q OR SO PACKAGE
(TOP VIEW)


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