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DAC34SH84IZAY データシート(PDF) 10 Page - Texas Instruments |
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DAC34SH84IZAY データシート(HTML) 10 Page - Texas Instruments |
10 / 77 page DAC34SH84 SLAS808B – FEBRUARY 2012 – REVISED JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N(1) Logic-high differential VA,B+ input voltage 200 mV threshold Logic-low differential VA,B– input voltage –200 mV threshold VCOM Input common mode 1 1.2 1.6 V ZT Internal termination 85 110 135 Ω LVDS input CL 2 pF capacitance Interleaved LVDS fINTERL 1500 MSPS data transfer rate fDATA Input data rate 750 MSPS CLOCK INPUT (DACCLKP/N) Duty cycle 40% 60% Differential voltage(2) |DACCLKP - DACCLKN| 0.4 1 V Internally biased common-mode 0.2 V voltage Single-ended swing –0.4 V level DACCLKP/N input 1500 MHz frequency OUTPUT STROBE (OSTRP/N) fOSTR = fDACCLK / (n × 8 × interp) where n is any positive fDACCLK / fOSTR Frequency integer, (8× MHz fDACCLK is DACCLK frequency in MHz interp) Duty cycle 50% Differential voltage |OSTRP-OSTRN| 0.4 1.0 V Internally biased common-mode 0.2 V voltage Single-ended swing –0.4 V level CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA High-level input 0.7 × VIH V voltage IOVDD2 Low-level input 0.3 × VIL V voltage IOVDD2 High-level input IIH –40 40 µA current Low-level input IIL –40 40 µA current CMOS input CI 2 pF capacitance IOVDD2 – Iload = –100 μA V 0.2 VOH ALARM, SDO, SDIO 0.8 × Iload = –2 mA V IOVDD2 Iload = 100 μA 0.2 V VOL ALARM, SDO, SDIO Iload = 2 mA 0.5 V (1) See LVDS INPUTS section for terminology. (2) Driving the clock input with a differential voltage lower than 1 V may result in degraded performance. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DAC34SH84 |
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