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DESCRIPTION

DAC5675A

SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005

14-Bit, 400MSPS Digital-to-Analog Converter

•

•

400MSPS Update Rate

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Package: 48-Pin HTQFP PowerPad™,

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LVDS-Compatible Input Interface

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Spurious-Free Dynamic Range (SFDR) to

Nyquist:

– 69dBc at 70MHz IF, 400MSPS

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Cellular Base Transceiver Station Transmit

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W-CDMA Adjacent Channel Power Ratio

Channel:

(ACPR):

– CDMA: WCDMA, CDMA2000, IS-95

– 73dBc at 30.72MHz IF, 122.88MSPS

– TDMA: GSM, IS-136, EDGE/GPRS

– 71dBc at 61.44MHz IF, 245.76MSPS

– Supports Single-Carrier and Multicarrier

Applications

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Differential Scalable Current Sink Outputs:

2mA to 20mA

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Test and Measurement: Arbitrary Waveform

Generation

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On-Chip 1.2V Reference

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Direct Digital Synthesis (DDS)

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Single 3.3V Supply Operation

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Cable Modem Headend

The DAC5675A is a 14-bit resolution high-speed digital-to-analog converter. The DAC5675A is designed for

high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital

synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A has

excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes the DAC5675A

well-suited for multicarrier transmission in TDMA- and CDMA-based cellular base transceiver stations (BTSs).

single-ended and differential applications. The output current can be directly fed to the load with no additional

The DAC5675A comprises a low-voltage differential signaling (LVDS) interface for high-speed digital data input.

LVDS features a low differential voltage swing with a low constant power consumption across frequency,

allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference

(EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for

high-speed interfacing between the DAC5675A and high-speed low-voltage CMOS ASICs or FPGAs. The

DAC5675A current-sink-array architecture supports update rates of up to 400MSPS. On-chip edge-triggered

input latches provide for minimum setup and hold times, thereby relaxing interface timing.

The DAC5675A has been specifically designed for a differential transformer-coupled output with a 50

Ω doubly-

terminated load. With the 20mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power

of 4dBm) and 1:1 impedance ratio transformer (–2dBm) are supported. The last configuration is preferred for

optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and

An accurate on-chip 1.2V temperature-compensated bandgap reference and control amplifier allows the user to

adjust this output current from 20mA down to 2mA. This provides 20dB gain range control capabilities.

Alternatively, an external reference voltage may be applied. The DAC5675A features a SLEEP mode, which

reduces the standby power to approximately 18mW.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPad is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2004–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.