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SM320C26BGBM データシート(PDF) 3 Page - Texas Instruments |
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SM320C26BGBM データシート(HTML) 3 Page - Texas Instruments |
3 / 40 page SMJ320C26 DIGITAL SIGNAL PROCESSOR SGUS 016A – AUGUST 1990 – REVISED AUGUST 2001 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PIN NOMENCLATURE NAME I/O/Z† DEFINITION VCC I 5-V supply pins. VSS I Ground pins. X1 O Output from internal oscillator for crystal. X2/CLKIN I Input to internal oscillator from crystal or external clock. CLKOUT1 O Master clock output (crystal or CLKIN frequency/4). CLKOUT2 O A second clock output signal. D15–D0 I/O/Z 16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data and I/O spaces. A15–A0 O/Z 16-bit address bus A15 (MSB) through A0 (LSB). PS, DS, IS O/Z Program, data and I/O space select signals. R/W O/Z Read/write signal. STRB O/Z Strobe signal. RS I Reset input. INT2, INT1, INT0 I External user interrupt inputs. MP/MC I Microprocessor/microcomputer mode select pin. MSC O Microstate complete signal. IACK O Interrupt acknowledge signal. READY I Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction is complete. BR O Bus request signal. Asserted when the SMJ320C26 requires access to an external global data memory space. XF O External flag output (latched software – programmable signal). HOLD I Hold input. When asserted, SMJ320C26 goes into an idle mode and places the data address and control lines in the high-impedance state. HOLDA O Hold acknowledge signal. SYNC I Synchronization input. BIO I Branch control input. Polled by BIOZ instruction. DR I Serial data receive input. CLKR I Clock input for serial port receiver. FSR I Frame synchronization pulse for receive input. DX O/Z Serial data transmit output. CLKX I Clock input for serial port transmitter. FSX I/O/Z Frame synchronization pulse for transmit. May be configured as either an input or an output. † I/O/Z denotes input/output/high-impedance state. |
同様の部品番号 - SM320C26BGBM |
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同様の説明 - SM320C26BGBM |
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