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DESCRIPTION

136

-128

-144

-160

0.4

0.8

1.2

1.6

2.0

2.4

2.8

170

153

119

102

85

68

51

34

17

0

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

Process = Nominal

Process = Nominal

-80

-96

-112

-32

-48

-64

0

-16

SN74AVC16269

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER

WITH 3-STATE OUTPUTS

SCES152G – DECEMBER 1998 – REVISED MAY 2005

•

Overvoltage-Tolerant Inputs/Outputs Allow

Mixed-Voltage-Mode Data Communications

•

Member of the Texas Instruments Widebus™

Family

•

Operation

•

EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

DOC™ (Dynamic Output Control) Circuit

Dynamically Changes Output Impedance,

•

Package Options Include Plastic Thin Shrink

Resulting in Noise Reduction Without Speed

Small-Outline (DGG) and Thin Very

Degradation

Small-Outline (DGV) Packages

•

Dynamic Drive Capability Is Equivalent to

A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output

impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows

the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a

high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family

Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry

Technology and Applications, literature number SCEA009.

Figure 1. Output Voltage vs Output Current

The SN74AVC16269 is used in applications in which two separate ports must be multiplexed onto, or

demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous

DRAMs and high-speed microprocessors.

Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the

appropriate clock-enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit

words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage

register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output

permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, EPIC, DOC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 1998–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.