ADC1015S125HN-C1 datasheet(1/40 Pages) IDT

部品番号	ADC1015S125HN-C1

部品情報	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

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1. General description

The ADC1015S is a single channel 10-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performances and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1015S is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,

because of a separate digital output supply.

The ADC1015S supports the Low Voltage Differential Signalling (LVDS) Double Data

Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the

user to easily configure the ADC.

The device also includes a SPI programmable full-scale to allow flexible input voltage

range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the

baseband to input frequencies of 170 MHz or more, the ADC1015S is ideal for use in

communications, imaging and medical applications - especially in high Intermediate

Frequency (IF) applications because of the integrated input buffer. The input buffer

ensures that the input impedance remains constant and low and the performance

consistent over a wide frequency range.

2. Features and benefits

ADC1015S series

Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps

with input buffer; CMOS or LVDS DDR digital outputs

Rev. 03 — 2 July 2012

Product data sheet



SNR, 61.7 dBFS / SFDR, 86 dBc



Input bandwidth, 600 MHz



Sample rate up to 125 Msps



Power dissipation, 635 mW at 80 Msps,

including analog input buffer



10-bit pipelined ADC core



Serial Peripheral Interface (SPI)



Clock input divided by 2 for less jitter

contribution



Duty cycle stabilizer



Integrated input buffer



Fast OuT-of-Range (OTR) detection



Flexible input voltage range:

1 V (p-p) to 2 V (p-p)



Offset binary, two’s complement, gray

code



CMOS or LVDS DDR digital outputs



Power-down mode and Sleep mode



Pin compatible with the ADC1415S

series, the ADC1215S series and the

ADC1115S125



HVQFN40 package

同様の部品番号 - ADC1015S125HN-C1

メーカー	部品番号	データシート	部品情報
NXP Semiconductors	ADC1015S125HN/C1	287Kb / 39P	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps Rev. 01 - 12 April 2010 Preliminary data sheet Rev. 01-12 April 2010

More results

同様の説明 - ADC1015S125HN-C1

メーカー	部品番号	データシート	部品情報
Renesas Technology Corp	ADC1015S	386Kb / 40P	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs 2 July 2012
NXP Semiconductors	ADC1010S	284Kb / 36P	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 01-9 April 2010
Renesas Technology Corp	ADC1010S	390Kb / 37P	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs 2 July 2012
Integrated Device Techn...	ADC1010S	386Kb / 37P	Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs
NXP Semiconductors	ADC1415S	288Kb / 39P	Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs Rev. 03-12 April 2010
NXP Semiconductors	ADC1215S	287Kb / 39P	Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs Rev. 01-12 April 2010
Integrated Device Techn...	ADC1215S	383Kb / 40P	Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
Renesas Technology Corp	ADC1215S	386Kb / 40P	Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs 2 July 2012
Integrated Device Techn...	ADC1415S	383Kb / 40P	Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
NXP Semiconductors	ADC1210S	288Kb / 36P	Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 01-9 April 2010