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DAC1617D1G0 データシート(PDF) 2 Page - Integrated Device Technology |
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DAC1617D1G0 データシート(HTML) 2 Page - Integrated Device Technology |
2 / 78 page DAC1617D1G0 3 © IDT 2012. All rights reserved. Preliminary data sheet Rev. 03 — 2 July 2012 2 of 78 Integrated Device Technology DAC1617D1G0 Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating 3. Applications Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communications: LMDS/MMDS, point-to-point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE) 4. Ordering information Embedded Numerically Controlled Oscillator (NCO) with 40-bit programmable frequency High resolution internal digital gain and offset control to support high performance IQ-modulator image rejection Embedded complex(I/Q) digital IF modulator Internal phase correction 1.8 V and 3.3 V power supplies Inverse (sin x) / x function LVDS DDR compatible input interface with on-chip 100 terminations Power-down mode and Sleep mode; 5-bit NCO low-power mode LVDS DDR input clock up to 370 MHz On-chip 1.25 V reference LVDS or LVPECL compatible DAC clock Industrial temperature range 40 C to +85 C Interleaved or folded I and Q data input mode 72 pins small form factor HVQFN package Table 1. Ordering information Type number Package Name Description Version DAC1617D1G0HN HVQFN72 plastic thermal enhanced very thin quad flat package; no leads; 72 terminals; body 10 10 0.85 mm SOT813-3 |
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