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SO/I

SCK

CS

Z

Z

1

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

Z

Timing Diagrams

SCK

CS

SO

t

1

t

3

t

2

t

4

SCK

CS

SO

t

5

t

5

SCK

CS

SO

TMP121-EP

TMP123-EP

SGLS315 – SEPTEMBER 2005

Figure 7. Data READ

The TMP121 and TMP123 are SPI-compatible. Figure 8 and Figure 9 describe the various timing requirements,

with parameters defined in Table 3.

Table 3. Timing Description

MIN

MAX

UNIT

SCK period

100

ns

SCK falling edge to output data delay

30

ns

CS to rising edge SCK set-up time

40

ns

CS to output data delay

30

ns

CS rising edge to output high impedance

30

ns

Figure 8. Output Data Timing Diagram

Figure 9. High Impedance Output Timing Diagram

7