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TPIC84000TPWPRQ1 データシート(PDF) 6 Page - Texas Instruments

部品番号 TPIC84000TPWPRQ1
部品情報  LOW-FREQUENCY ANTENNA DRIVER FOR PASSIVE START AND PASSIVE ENTRY
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ホームページ  http://www.ti.com
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background image
0
VS
0
VS/2
VS
Out 1
Out 2
Time
(µs)
Start
119
( V )
Data
0
1
1
0
1
0
239
358
478
597
717
4.2 kBaud (Manchester encoded "100")
VS/2
TPIC84134-Q1
SLDS176 – AUGUST 2010
www.ti.com
To function properly the following conditions must be satisfied:
The incoming clock (CLK_IN) has to be provided for at least 4 cycles of the internal clock after writing to
Configuration register via SPI
In the case of a wake up command (i.e. sleep bit = 0 in the Config Reg), CLK_IN has to be provided during
124 additional cycles of the internal clock for fault blanking after writing the Config Register. During that time:
Data1 buffer cannot be written to if sending mode bit in Config Reg is set to 1 (autosend mode).
SPI command "Start Transmission" cannot be programmed
In the case of CSR read and if a fault is cleared then, CLK_IN also has to be provided during a total of 128
clock cycles for the same reason of fault blanking.
CLK_IN electrical levels:
When the CLK_IN is OFF, the electrical level should be high (typically 5V)
The clock should be turned OFF after a low to high transition of CLK_IN
Sine Wave Generation
The sine wave generation block generates the 134.2 kHz sine wave from the internal clock. This sine wave is
used to generate the carrier frequency which is used for transmitting the signal as well as Destroy bits.
Note that the Destroy bits consist of bringing the selected channel to VS/2, transmitting a small number of bits
(1-4 programmable through SPI) at a reduced peak-to-peak voltage, then the channel is grounded again (HS off,
LS on). The purpose of the destroy bits is to actively stop any unwanted transmission signal that may be present
on the antenna due to coupling from the transmitting antenna.
For example, Figure 2 shows the first 6 Transmitted Bits (3 Manchester Bits) of a telegram together with three
destroy bits on the non-active outputs. The counter for start of destroy bits is set to 3, and it starts counting down
at the beginning of the transmission telegram denoted by "start" in the below diagram.
Figure 2. Transmitted Telegram Sample With Destroy Bits
6
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Product Folder Link(s): TPIC84134-Q1


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