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TPS28225TDRBRQ1 データシート(PDF) 9 Page - Texas Instruments |
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TPS28225TDRBRQ1 データシート(HTML) 9 Page - Texas Instruments |
9 / 34 page TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION SOIC-8 DRB-8 NAME 1 1 UGATE O Upper gate drive sink/source output. Connect to gate of high-side power N-Channel MOSFET. Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between 2 2 BOOT I/O this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. The PWM signal is the control input for the driver. The PWM signal can enter three distinct states 3 3 PWM I during operation, see the 3-state PWM Input section under DETAILED DESCRIPTION for further details. Connect this pin to the PWM output of the controller. 4 4 GND — Ground pin. All signals are referenced to this node. Exposed Thermal — Connect directly to the GND for better thermal performance and EMI die pad pad Lower gate drive sink/source output. Connect to the gate of the low-side power N-Channel 5 5 LGATE O MOSFET. 6 6 VDD I Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND. Enable/Power Good input/output pin with 1M Ω impedance. Connect this pin to HIGH to enable and LOW to disable the device. When disabled, the device draws less than 350 μA bias current. If the 7 7 EN/PG I/O VDD is below UVLO threshold or over temperature shutdown occurs, this pin is internally pulled low. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin 8 8 PHASE I provides a return path for the upper gate driver. TRUTH TABLE VDD FALLING > 3 V AND TJ < 150°C VDD RISING < 3.5 V EN/PG FALLING > 1.0 V PIN EN/PG RISING OR TJ > 160°C PWM > 1.5 V AND PWM SIGNAL SOURCE IMPEDANCE < 1.7 V PWM < 1 V TRISE/TFALL < 200 ns >40 k Ω FOR > 250ns (3-State)(1) LGATE Low Low High Low Low UGATE Low Low Low High Low EN/PG Low (1) To exit the 3-state condition, the PWM signal should go low. One Low PWM input signal followed by one High PWM input signal is required before re-entering the 3-state condition. Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 |
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同様の説明 - TPS28225TDRBRQ1 |
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