1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AUX

NC

A0

A1

SCL

SDA

PENIRQ

NC

VDD/REF

X+

Y+

X

-

Y

-

GND

NC

NC

TSC2007

TSC2007-Q1

www.ti.com

SBAS545

– SEPTEMBER 2011

PIN CONFIGURATION

PW PACKAGE

TSSOP-16

(TOP VIEW)

PIN ASSIGNMENTS

PIN NO.

PIN NAME

I/O

A/D

DESCRIPTION

1

VDD/REF

Supply voltage and external reference input

2

X+

I

A

X+ channel input

3

Y+

I

A

Y+ channel input

4

X

–

I

A

X

– channel input

5

Y

–

I

A

Y

– channel input

6

GND

Ground

7

NC

No connection

8

NC

No connection

9

NC

No connection

10

PENIRQ

O

D

Data available interrupt output. A delayed (process delay) pen touch detect. Pin polarity with active low.

11

SDA

I/O

D

Serial data I/O

Serial clock. This pin is normally an input, but acts as an output when the device stretches the clock to delay a bus

12

SCL

I/O

D

transfer.

13

A1

I

D

Address input bit 1

14

A0

I

D

Address input bit 0

15

NC

No connection

16

AUX

I

A

Auxiliary channel input

Copyright

© 2011, Texas Instruments Incorporated

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Product Folder Link(s): TSC2007-Q1