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SN74AUC32374ZKER データシート(PDF) 6 Page - Texas Instruments

部品番号 SN74AUC32374ZKER
部品情報  32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
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メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
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SN74AUC32374ZKER データシート(HTML) 6 Page - Texas Instruments

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Operating Characteristics
(1)
SN74AUC32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES475 – AUGUST 2003 – REVISED MAY 2005
T
A = 25°C
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
TEST
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
TYP
TYP
1 fdata = 5 MHz,
Outputs
Cpd(2)
Power
1 fclk = 10 MHz,
enabled,
(each
dissipation
1 fout = 5 MHz,
24
24
24.1
26.2
31.2
pF
1 output
output)
capacitance
OE = GND,
switching
CL = 0 pF
Outputs
1 fdata = 5 MHz,
disabled,
1 fclk = 10 MHz,
Power
Cpd
1 clock
fout = not
dissipation
7.5
7.5
8
9.4
13.2
pF
(Z)
and 1
switching,
capacitance
data
OE = VCC,
switching CL = 0 pF
1 fdata = 0 MHz,
Outputs
1 fclk = 10 MHz,
Cpd(3)
Power
disabled,
fout = not
(each
dissipation
clock
13.8
13.8
14
14.7
17.5
pF
switching,
clock)
capacitance
only
OE = VCC,
switching
CL = 0 pF
(1)
Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = [n * Cpd (each output)] + [y * Cpd (each clock)].
(2)
Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz
in this test, but its ICC component has been subtracted out).
(3)
Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz.
6


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