データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

SN74BCT8373DW データシート(PDF) 11 Page - Texas Instruments

部品番号 SN74BCT8373DW
部品情報  SCAN TEST DEVICE WITH OCTAL D-TYPE LATCHES
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  TI1 [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI1 - Texas Instruments

SN74BCT8373DW データシート(HTML) 11 Page - Texas Instruments

Back Button SN74BCT8373DW Datasheet HTML 7Page - Texas Instruments SN74BCT8373DW Datasheet HTML 8Page - Texas Instruments SN74BCT8373DW Datasheet HTML 9Page - Texas Instruments SN74BCT8373DW Datasheet HTML 10Page - Texas Instruments SN74BCT8373DW Datasheet HTML 11Page - Texas Instruments SN74BCT8373DW Datasheet HTML 12Page - Texas Instruments SN74BCT8373DW Datasheet HTML 13Page - Texas Instruments SN74BCT8373DW Datasheet HTML 14Page - Texas Instruments SN74BCT8373DW Datasheet HTML 15Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 21 page
background image
SN74BCT8373
SCAN TEST DEVICE
WITH OCTAL DTYPE LATCHES
SCBS471 − JUNE 1990 − REVISED JUNE 1994
2−11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned
into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into
the output BSCs is applied to the device output terminals. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.
control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device output terminals are placed in the high-impedance state,
the device input terminals remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device
output terminals. The device operates in the test mode.
boundary run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The four test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, and simultaneous PSA and PRPG (PSA/PRPG).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches may be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device output
terminals on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and
is applied to the inputs of the normal on-chip logic. Data appearing at the device input terminals is not captured
in the input BSCs. The device operates in the test mode.


同様の部品番号 - SN74BCT8373DW

メーカー部品番号データシート部品情報
logo
Texas Instruments
SN74BCT8373A TI-SN74BCT8373A Datasheet
473Kb / 26P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
SN74BCT8373ADW TI-SN74BCT8373ADW Datasheet
473Kb / 26P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
SN74BCT8373ADWE4 TI-SN74BCT8373ADWE4 Datasheet
473Kb / 26P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
SN74BCT8373ADWR TI-SN74BCT8373ADWR Datasheet
473Kb / 26P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
SN74BCT8373ADWRE4 TI-SN74BCT8373ADWRE4 Datasheet
473Kb / 26P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
More results

同様の説明 - SN74BCT8373DW

メーカー部品番号データシート部品情報
logo
Texas Instruments
SN54BCT8373A TI-SN54BCT8373A Datasheet
473Kb / 26P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES
SN54BCT8374A TI-SN54BCT8374A Datasheet
474Kb / 26P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SN54BCT8374A TI-SN54BCT8374A_08 Datasheet
644Kb / 28P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SN54BCT8244A TI-SN54BCT8244A Datasheet
472Kb / 26P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL BUFFERS
SN54BCT8244A TI-SN54BCT8244A_07 Datasheet
612Kb / 28P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL BUFFERS
SN54BCT8244A TI-SN54BCT8244A_08 Datasheet
642Kb / 28P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL BUFFERS
logo
Unisonic Technologies
U74AHCT373 UTC-U74AHCT373_15 Datasheet
234Kb / 6P
   OCTAL TRANSPARENT D-TYPE LATCHES WITH
U74HCT373 UTC-U74HCT373_15 Datasheet
237Kb / 6P
   OCTAL TRANSPARENT D-TYPE LATCHES WITH
logo
Texas Instruments
SN54BCT8245A TI-SN54BCT8245A Datasheet
309Kb / 22P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS
SN54BCT8240A TI-SN54BCT8240A Datasheet
473Kb / 26P
[Old version datasheet]   SCAN TEST DEVICES WITH OCTAL INVERTING BUFFERS
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com