TPIC5424L

HBRIDGE LOGICLEVEL POWER DMOS ARRAY

SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994

Copyright

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

description

The TPIC5424L is a monolithic logic-level power

DMOS array that consists of four electrically

isolated N-channel enhancement-mode DMOS

transistors, two of which are configured with a

common source.

The TPIC5424L is offered in a 16-pin thermally

enhanced dual-in-line (NE) package and a 20-pin

wide-body surface-mount (DW) package. The

TPIC5424L is characterized for operation over the

case temperature range of − 40

°C to 125°C.

schematic

D1

DRAIN3

D2

Z1

Z3

Z2

Z4

GND, SOURCE2, SOURCE4

GATE3

DRAIN4

GATE4

SOURCE3

DRAIN1

GATE1

SOURCE1

DRAIN2

GATE2

Q1

Q2

Q4

Q3

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

GND

SOURCE4/GND

GATE4

NC

DRAIN4

SOURCE3

DRAIN3

GATE3

NC

NC

SOURCE2/GND

GATE2

NC

NC

DRAIN2

SOURCE1

DRAIN1

GATE1

NC

NC

DW PACKAGE

(TOP VIEW)

NC − No internal connection

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DRAIN2

SOURCE2/GND

GATE2

GND

GND

GATE4

SOURCE4/GND

DRAIN4

SOURCE1

DRAIN1

GATE1

GND

GND

GATE3

DRAIN3

SOURCE3

NE PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.