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74HCT373BQ-Q100 データシート(PDF) 10 Page - NXP Semiconductors |
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74HCT373BQ-Q100 データシート(HTML) 10 Page - NXP Semiconductors |
10 / 24 page 74HC_HCT373_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 10 August 2012 10 of 24 NXP Semiconductors 74HC373-Q100; 74HCT373-Q100 Octal D-type transparent latch; 3-state 10. Dynamic characteristics Table 8. Dynamic characteristics 74HC373-Q100 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit Tamb =25 C tpd propagation delay Dn to Qn; see Figure 8 [1] VCC = 2.0 V - 41 150 ns VCC = 4.5 V - 15 30 ns VCC =5V; CL =15pF - 12 - ns VCC = 6.0 V - 12 26 ns LE to Qn; see Figure 9 VCC = 2.0 V - 50 175 ns VCC = 4.5 V - 18 35 ns VCC =5V; CL =15pF - 15 - ns VCC = 6.0 V - 14 30 ns ten enable time OE to Qn; see Figure 10 [2] VCC = 2.0 V - 44 150 ns VCC = 4.5 V - 16 30 ns VCC = 6.0 V - 13 26 ns tdis disable time OE to Qn; see Figure 10 [3] VCC = 2.0 V - 47 150 ns VCC = 4.5 V - 17 30 ns VCC = 6.0 V - 14 26 ns tt transition time Qn; see Figure 8 and Figure 9 [4] VCC = 2.0 V - 14 60 ns VCC = 4.5 V - 5 12 ns VCC = 6.0 V - 4 10 ns tW pulse width LE HIGH; see Figure 9 VCC = 2.0 V 80 17 - ns VCC = 4.5 V 16 6 - ns VCC = 6.0 V 14 5 - ns tsu set-up time Dn to LE; see Figure 11 VCC = 2.0 V 50 14 - ns VCC = 4.5 V 10 5 - ns VCC = 6.0 V 9 4 - ns th hold time Dn to LE; see Figure 11 VCC = 2.0 V +5 8- ns VCC = 4.5 V +5 3- ns VCC = 6.0 V +5 2- ns CPD power dissipation capacitance per latch; VI =GND to VCC [5] -45 -pF |
同様の部品番号 - 74HCT373BQ-Q100 |
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同様の説明 - 74HCT373BQ-Q100 |
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