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TPIC5323LD データシート(PDF) 4 Page - Texas Instruments |
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TPIC5323LD データシート(HTML) 4 Page - Texas Instruments |
4 / 13 page TPIC5323L 3-CHANNEL INDEPENDENT GATE-PROTECTED SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(on) Turn-on delay time 34 50 td(off) Turn-off delay time VDD = 25 V, RL = 50 Ω,tr1 = 10 ns, 50 70 ns tr2 Rise time DD , tf1 = 10 ns, L , See Figure 2 r1 , 20 30 ns tf2 Fall time 15 25 Qg Total gate charge V48 V I 500 A V5 V 2 2.45 Qgs(th) Threshold gate-to-source charge VDS = 48 V, See Figure 3 ID = 500 mA, VGS = 5 V, 0.3 0.95 nC Qgd Gate-to-drain charge See Figure 3 1.2 1.48 LD Internal drain inductance 5 nH LS Internal source inductance 5 nH Rg Internal gate resistance 0.25 Ω thermal resistance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R θJA Junction-to-ambient thermal resistance See Notes 4 and 7 115 R θJB Junction-to-board thermal resistance See Notes 5 and 7 64 °C/W R θJP Junction-to-pin thermal resistance See Notes 6 and 7 33 NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink. 5. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board. 6. Package mounted in intimate contact with infinite heatsink. 7. All outputs with equal power PARAMETER MEASUREMENT INFORMATION † IRM = maximum recovery current ‡ The above waveform is representative of D1, D2, and D3 in shape only. Time – ns 0 50 100 150 200 250 300 350 400 450 500 1 0.5 0 – 0.5 – 1 – 1.5 – 2 – 2.5 – 3 IRM† trr(SD) Shaded Area = QRR Reverse di/dt = 100 A/ µs TJ = 25°C Z1, Z2, and Z3‡ 25% of IRM† Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode |
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