– 6 –

CXA1843Q

Timing Chart

MCLK(Pin 31)

(TTL)

(0 to –2V)

S/H CLK

(Not output to outside)

S/H OUT (Pin 11)

(0 to –2V)

A/D CLK (Pin 22)

(PECL)

A/D output (CXA1844Q)

(TTL)

MCLK

(Clock pulse for the

device next to the ADC

in order to latch the

A/D output)

N

N + 1

N + 2

Tsd

Hold

taqr

tdr

N – 1

tdf

taqf

2Vp-p

90%

10%

6ns

DN – 3

Th

Threshold

voltage =

1.5V

Threshold

voltage =

Threshold

voltage =

1.5V

Threshold

voltage =

1.5V

Threshold

voltage

DN – 2

DN – 1

DN

10%

90%

N + 2

N + 1

N

Hold

Sample

Hold

Sample

Hold

Tsd

Tsd

Sample

MCLK:

System master clock.

S/H CLK:

This clock actuates the internal sample-and-hold circuit.

The internal clock pulse circuit generates the S/H CLK, which is not output outside the IC.

A/D CLK:

This clock actuates the A/D converter. The internal clock buffer circuit generates the A/D CLK.

This clock has the level where +5V is shifted from the ECL level.

S/H CLKIN input clock width

Tsd:

S/H sampling delay for the S/H internal clock

Time interval between MCLK rise and A/D CLK fall

Time interval between MCLK rise and S/H CLK rise

Time interval between MCLK rise and S/H CLK fall

10%/90% falling output delay of S/H from MCLK rise

10%/90% rising output delay of S/H from MCLK rise

Ts:

Setup time of A/D output and MCLK

Th:

Hold time of A/D output and MCLK