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SMB206A データシート(PDF) 6 Page - Summit Microelectronics, Inc.

部品番号 SMB206A
部品情報  Dual Programmable Buck Regulators with Integrated MOSFETs and Digital Control
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メーカー  SUMMIT [Summit Microelectronics, Inc.]
ホームページ  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

SMB206A データシート(HTML) 6 Page - Summit Microelectronics, Inc.

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SMB206A/7A/8A
Preliminary
SUMMIT Microelectronics, Inc.
2147 2.4 2/23/2012
6
OUTPUT STATES
EN0 Pin
EN1 Pin
CH0 enable bit
CH1 enable bit
Chip State
Output Behavior
CH0
CH1
Low
Low
X
X
Shutdown
Disabled
Disabled
Low
High
X
0
Shutdown
Disabled
Disabled
High
Low
0
X
Standby
Disabled
Disabled
Low
High
X
1
Shutdown
Disabled
Enabled
High
Low
1
X
Active
Enabled
Disabled
High
High
0
0
Standby
Disabled
Disabled
High
High
0
1
Active
Disabled
Enabled
High
High
1
0
Active
Enabled
Disabled
High
High
1
1
Active
Enabled
Enabled
Note: “X” denotes a “Don’t Care” state
OUTPUT SEQUENCING
Auto Sequence
[02h bits3:2]
Output Behavior*
0
0
CH0/CH1 respond independently to enable pins/bits, no auto-sequence
0
1
CH1 is dependent on CH0 state. CH1 always turns on after and turns off before CH0 (based on PGOOD signals)**
1
0
CH0 is dependent on CH1 state. CH0 always turns on after and turns off before CH1 (based on PGOOD signals)**
1
1
CH0 and CH1 turn on and off together**
*Power down timing is not specifically controlled and is dependent on load current and output capacitance - slew rate is not guaranteed. Assumes
input UVLO is cleared. If auto-sequence bit are other than 00b then fault conditions (OC, OT etc.) may shutdown both outputs.
**Assumes EN pins and enable bits are in the intended states per the Output State Table.
PGOOD/RESET
Assignment
[02h bits7:6]
VOUT0
VOUT1
PGOOD/RESET Output
00
VOUT0 < VPG0
VOUT1 < VPG1
Low
VOUT0 < VPG0
VOUT1 > VPG1
Low
VOUT0 > VPG0
VOUT1 < VPG1
Low
VOUT0 > VPG0
VOUT1 > VPG1
High
01
Don’t Care
VOUT1 < VPG1
Low
Don’t Care
VOUT1 > VPG1
High
10
VOUT0 < VPG0
Don’t Care
Low
VOUT0 > VPG0
Don’t Care
High
11
Don’t Care
Don’t Care
High
OUTPUT STATE/SEQUENCE LOGIC TABLES
POWERGOOD/RESET OUTPUT LOGIC TABLE


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