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ADC08D502NOPB データシート(PDF) 3 Page - Texas Instruments |
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ADC08D502NOPB データシート(HTML) 3 Page - Texas Instruments |
3 / 43 page GND VA 50k OutEdge/DDR/SDATA GND VA OUTV/SCLK VA GND VCMO GND VINI- VINI+ GND 12 16 FSR/ECE CLK+ CLK- GND VINQ+ VINQ- GND PD GND ADC08D502 20 24 28 CAL VBG REXT 32 31 30 29 27 26 25 23 22 21 19 18 17 15 14 13 11 10 1 4 8 9 7 6 5 3 2 DQ7+ DQ7- OR+ OR- DCLK- DCLK+ DI7- DI7+ DI6- DI6+ DR GND DI5- DI5+ DI4- DI4+ DI3- DI3+ DI2- DI2+ 71 81 86 91 96 DQ4+ DQ4- DQ5+ DQ5- DR GND DQ6+ DQ6- DQ2+ DQ2- DQ3+ DQ3- 76 66 65 67 68 69 70 73 72 74 75 78 77 79 80 83 82 84 85 88 87 89 90 93 92 94 95 VA VA VA PDQ VA VA VA VA DCLK_RST VDR VDR * ADC08D502 www.ti.com SNOSC85 – AUGUST 2012 Pin Configuration * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit Description Output Voltage Amplitude and Serial Interface Clock. Tie this pin high for normal differential DCLK and data amplitude. Ground this 3 OutV / SCLK pin for a reduced differential output amplitude and reduced power consumption. When the extended control mode is enabled, this pin functions as the SCLK input which clocks in the serial data. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC08D502 |
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同様の説明 - ADC08D502NOPB |
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