ADC08D502NOPB datasheet(5/43 Pages) TI1

部品番号	ADC08D502NOPB

部品情報	ADC08D502 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

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VD

DGND

GND

VA

200k

8 pF

VCM

Enable AC

Coupling

50k

VA

AGND

VA

AGND

50k

Control from VCMO

VCMO

100

VA

AGND

VA

AGND

100

VBIAS

50k

ADC08D502

www.ti.com

SNOSC85 – AUGUST 2012

Pin Functions

Pin No.

Symbol

Equivalent Circuit

Description

LVDS Clock input pins for the ADC. The differential clock signal

18

CLK+

must be a.c. coupled to these pins. The input signal is sampled on

19

CLK-

the falling edge of CLK+.

11

VINI+

10

VINI−

Analog signal inputs to the ADC. The differential full-scale input

.

range is 650 mVP-P when the FSR pin is low, or 870 mVP-P when

22

VINQ+

the FSR pin is high.

23

VINQ−

Common Mode Voltage. This pin is the common mode output in

d.c. coupling mode and also serves as the a.c. coupling mode

select pin. When d.c. coupling is used, the voltage output at this pin

7

VCMO

is required to be the common mode input voltage at VIN+ and VIN−

when d.c. coupling is used. This pin should be grounded when a.c.

coupling is used at the analog inputs. This pin is capable of

sourcing or sinking 100

μA.

31

VBG

Bandgap output voltage capable of 100

μA source/sink.

Calibration Running indication. This pin is at a logic high when

126

CalRun

calibration is running.

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同様の部品番号 - ADC08D502NOPB

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	ADC08D502	902Kb / 48P	[Old version datasheet] High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

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