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74LVX86M データシート(PDF) 1 Page - Fairchild Semiconductor |
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74LVX86M データシート(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page ©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVX86 Rev. 1.4.0 February 2008 74LVX86 Low Voltage Quad 2-Input Exclusive-OR Gate Features ■ Input voltage level translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance General Description The LVX86 contains four 2-input exclusive-OR gates. The inputs tolerate voltages up to 7V allowing the inter- face of 5V systems to 3V systems. Ordering Information Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Pin Description Logic Symbol IEEE/IEC Order Number Package Number Package Description 74LVX86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX86SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX86MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description A0–A3 Inputs B0–B3 Inputs O0–O3 Outputs |
同様の部品番号 - 74LVX86M_08 |
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同様の説明 - 74LVX86M_08 |
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