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74LVX132MTC データシート(PDF) 1 Page - Fairchild Semiconductor |
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74LVX132MTC データシート(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page ©1996 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVX132 Rev. 1.4.0 February 2008 74LVX132 Low Voltage Quad 2-Input NAND Schmitt Trigger Features ■ Input voltage level translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance General Description The LVX132 contains four 2-input NAND Schmitt Trigger Gates. The pin configuration and function are the same as the LVX00 but the inputs have hysteresis between the positive-going and negative-going input thresholds, which are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals, thus providing greater noise margins than conventional gates. The inputs tolerate voltages up to 7V allowing the inter- face of 5V systems to 3V systems. Ordering Information Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Package Number Package Description 74LVX132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
同様の部品番号 - 74LVX132MTC_08 |
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同様の説明 - 74LVX132MTC_08 |
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