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AD9915 データシート(PDF) 10 Page - Analog Devices |
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AD9915 データシート(HTML) 10 Page - Analog Devices |
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10 / 48 page  AD9915 Data Sheet Rev. A | Page 10 of 48 Pin No. Mnemonic I/O1 Description 12 D8/A0 I/O Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. 18 D4/SYNCIO I Parallel Port Pin/Serial Port Synchronization Pin. This pin is D4 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin is used to reset the serial port. 19 D3/SDO I/O Parallel Port Pin/Serial Data Output This pin is D3 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin is used for readback mode for serial operation. 20 D2/SDIO/WR I/O Parallel Port Pin/Serial Data Input and Output/Write Input. This pin is D2 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin is used for the SDIO for serial operation. If parallel mode is enabled, this pin is used to write to change the values of the internal registers. 21 D1/SCLK/RD I Parallel Port Pin/Serial Clock/Read Input. This pin is D1 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin is used for SCLK for serial operation. If parallel mode is enabled, this pin is used to read back the value of the internal registers. 22 D0/CS/PWD I Parallel Port Pin/Chip Select/Parallel Width. This pin is D0 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin is used for the chip select for serial operation. If parallel mode is enabled, this pin is used to set either 8-bit data or16-bit data. 6, 23, 73 DVDD (1.8V) I Digital Core Supplies (1.8 V). 7, 17, 24, 74, 84 DGND I Digital Ground. 16, 83 DVDD_I/O (3.3V) I Digital Input/Output Supplies (3.3 V). 32, 56, 57 AVDD (1.8V) I Analog Core Supplies (1.8 V). 33, 35, 37, 38, 44, 46, 49, 51 AGND I Analog Ground. 34, 36, 39, 40, 43, 47, 50, 52, 53, 60 AVDD (3.3V) I Analog DAC Supplies (3.3 V). 25, 26, 27 PS0 to PS2 I Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the current contents of all I/O buffers to the corresponding registers. State changes should be set up on the SYNC_CLK pin (Pin 82). 28, 29, 30, 31 F0 to F3 I Function Pins. Digital inputs. The state of these pins determines if a serial or parallel interface is used. In addition, the function pins determine how the 32-bit parallel data-word is partitioned for FSK, PSK, or ASK modulation mode. 41 AOUT O DAC Complementary Output Source. Analog output (voltage mode). Internally connected through a 50 Ω resistor to AVDD (3.3V). 42 AOUT O DAC Output Source. Analog output (voltage mode). Internally connected through a 50 Ω resistor to AVDD (3.3V). 45 DAC_BP I DAC Bypass Pin. Provides access to the common control node of the DAC current sources. Connecting a capacitor between this pin and ground can improve noise performance at the DAC output. 48 DAC_RSET O Analog Reference. This pin programs the DAC output full-scale reference current. Connect a 3.3 kΩ resistor to AGND. 54 REF_CLK I Complementary Reference Clock Input. Analog input. 55 REF_CLK I Reference Clock Input. Analog input. 58 LOOP_FILTER O External PLL Loop Filter Node. 59 REF O Local PLL Reference Supply. Typically at 2.05 V. 61 SYNC_OUT O Digital Synchronization Output. Used to synchronize multiple chips. 62 SYNC_IN I Digital Synchronization Input. Used to synchronize multiple chips. 63 DRCTL I Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down). 64 DRHOLD I Ramp Hold. Digital input (active high). Pauses the sweep when active. 65 DROVER O Ramp Over. Digital output (active high). This pin switches to Logic 1 when the digital ramp generator reaches its programmed upper or lower limit. 66 OSK I Output Shift Keying. Digital input (active high). When the OSK features are placed in either manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles the multiplier between 0 (low) and the programmed amplitude scale factor (high). In automatic mode, a low sweeps the amplitude down to zero and a high sweeps the amplitude up to the amplitude scale factor. |
同様の部品番号 - AD9915 |
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同様の説明 - AD9915 |
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