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FM23MLD16 データシート(PDF) 5 Page - Cypress Semiconductor |
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FM23MLD16 データシート(HTML) 5 Page - Cypress Semiconductor |
5 / 13 page FM23MLD16 - 512Kx16 FRAM (multi die) Rev. 2.0 June 2012 Page 5 of 13 locations may be accessed without the need to toggle the CE pins. For fast access reads, once the first data byte is driven onto the bus, the column address inputs A(1:0) may be changed to a new value. A new data byte is then driven to the DQ pins no later than tAAP, which is less than half the initial read access time. For fast access writes, the first write pulse defines the first write access. While the device is selected (both chip enables asserted), a subsequent write pulse along with a new column address provides a page mode write access. Precharge Operation The precharge operation is an internal condition in which the state of the memory is being prepared for a new access. Precharge is user-initiated by driving at least one of the chip enable signals to an inactive state. It must remain high for at least the minimum precharge time tPC. SRAM Drop-In Replacement The FM23MLD16 has been designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require the CE pins to toggle for each new address. Both CE pins may remain active indefinitely. When both CE pins are active, the device automatically detects address changes and a new access is begun. This functionality allows the chip enable pins to be tied active (/CE1 grounded, CE2 tied to VDD) as you might with an SRAM. It also allows page mode operation at speeds up to 33MHz. A typical application is shown in Figure 2. It shows a pullup resistor on /CE1 which will keep the pin high during power cycles assuming the MCU/MPU pin tri- states during the reset condition. The pullup resistor value should be chosen to ensure the /CE1 pin tracks VDD yet a high enough value that the current drawn when /CE1 is low is not an issue. Although not required, it is recommended that CE2 be tied to VDD if the controller provides an active-low chip enable. Figure 2. Typical Application using Pullup Resistor on /CE1 For applications that require the lowest power consumption, the /CE1 signal should be active only during memory accesses. The FM23MLD16 draws supply current while /CE1 is low, even if addresses and control signals are static. While /CE1 is high, the device draws no more than the maximum standby current ISB. Note that if /CE1 is grounded and CE2 tied to VDD, the user must be sure /WE is not low at powerup or powerdown events. If the chip is enabled and /WE is low during power cycles, data corruption will occur. Figure 3 shows a pullup resistor on /WE which will keep the pin high during power cycles assuming the MCU/MPU pin tri-states during the reset condition. The pullup resistor value should be chosen to ensure the /WE pin tracks VDD yet a high enough value that the current drawn when /WE is low is not an issue. A 10Kohm resistor draws 330uA when /WE is low and VDD=3.3V. Figure 3. Use of Pullup Resistor on /WE The /UB and /LB byte select pins are active for both read and write cycles. They may be used to allow the device to be wired as a 1Mx8 memory. The upper and lower data bytes can be tied together and controlled with the byte selects. Individual byte enables or the next higher address line A(19) may be available from the system processor. Figure 4. FM23MLD16 Wired as 1Mx8 CE2 CE1 WE OE A(18:0) DQ(15:0) FM23MLD16 VDD MCU/ MPU R CE2 CE1 WE OE A(18:0) DQ(15:0) FM23MLD16 VDD MCU/ MPU R |
同様の部品番号 - FM23MLD16 |
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同様の説明 - FM23MLD16 |
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