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FM25VN02-DG データシート(PDF) 11 Page - Cypress Semiconductor

部品番号 FM25VN02-DG
部品情報  256Kb Serial 3V F-RAM Memory
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM25VN02-DG データシート(HTML) 11 Page - Cypress Semiconductor

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FM25V02 - 256Kb SPI FRAM
Rev. 3.0
Jan. 2012
Page 11 of 17
Figure 15. Read Serial Number
Endurance
The FM25V02 and FM25VN02 device is capable of
being accessed at least 10
14 times, reads or writes. An
F-RAM memory operates with a read and restore
mechanism. Therefore, an endurance cycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A14-A3 and column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 4K rows of
64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 40MHz clock rate.
Table 7. Time to Reach 100 Trillion Cycles for Repeating 64-byte Loop
SCK Freq
(MHz)
Endurance
Cycles/sec.
Endurance
Cycles/year
Years to Reach
10
14 Cycles
40
74,620
2.35 x 10
12
42.6
20
37,310
1.18 x 10
12
85.1
10
18,660
5.88 x 10
11
170.2
5
9,330
2.94 x 10
11
340.3
S
C
D
Q
Byte 7
Byte 6
. . .
C3h
. . . . . . .
Byte 1
Byte 0


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