LC08101CT

No.A2010-6/20

Start and stop conditions

a data transfer operation.

When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is

started when SDA is changed from high to low while SCL and SDA are high.

Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is

high.

Data transfer and acknowledgement response

After the start condition is generated, data is transferred one byte (8 bits) at a time. Any number of data bytes can be

transferred consecutively.

An ACK signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. The

transmission of an ACK signal is performed by setting the receiving side SDA to low after SDA at the sending side is

released immediately after the clock pulse of SCL bit 8 in the data transferred has fallen low.

After the receiving side has sent the ACK signal, if the next byte transfer operation is to receive only the byte, the

receiving side releases SDA on the falling edge of the 9th clock of SCL.

transfer data is allocated to the 7-bit slave address and to the command (R/W) which specifies the direction of

subsequent data transfer.

The READ function of the LC08101CT Driver area provides only the functionality to test the BUSY state.

7-bit address data is transferred sequentially starting at the MSB and the second and subsequent bytes are written if the

state of the 8th bit is low and read if the state is high.

In the LC08101CT Driver area, the slave address is stipulated to be “1110010.”

WRITE mode timing

ts2

th2

SCL

SDA

th1

th3

SCL

SDA

Start condition

Stop condition

M

S

B

L

S

B

A

C

K

L

S

B

A

C

K

M

S

B

M

S

B

L

S

B

A

C

K

W

X

SCL

SDA

Start

Stop

XXXXXX0

0

0

1

1

000

0

0

0

0

0

000

1

Slave address

Register address

Data