LC72722PMS

No. A2156-11/18

(7) Crystal oscillator frequency selection (1bit) : XS

XS = 0 : 4.332MHz (Initial value : XS = 0)

XS = 1 : 8.664MHz

(8) Demodulation circuit phase control (2bits) : PL0, PL1

PL0

PL1

Demodulation circuit phase control

0

0/1

 Normal operation  when ARI presence or absence is unclear.

1

0

If the circuit determines that the ARI signal is absent : 90

 phase

1

If the circuit determines that the ARI signal is present : 0

 phase

Initial values : PL0 = 0, PL1 = 1

the RDS data by automatically controlling the demodulation phase with respect to the reproduced carrier.

However, the initial phase following a synchronization reset is set by PL1.

2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90

 (PL1 = 0) or

0

 (PL1 = 1), allowing RDS data to be reproduced. When ARI is not present, PL1 should be set to 0, since the

RDS data is reproduced by detecting at a phase of 90

 with respect to the reproduced carrier. When ARI is present,

PL1 should be set to 1, since detection is at 0

. In cases where the ARI presence is known in advance, more stable

reproduction can be achieved by fixing the demodulation phase in this manner.

(9) RDS/RBDS(MMBS) selection (1bit) : RM

RM

RBDS

Decoding method

0

None

Only RDS data is decoded correctly (Offset word E is not detected.)

1

Provided

RDS and MMBS data is decoded correctly (Offset word E is also detected.)

Initial value : RM=0

(10) Output pin settings (3bits) : PT0 to PT2

These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins

MODE

P

T

0

P

T

1

P

T

2

T3

T4

T5

T6

T7

RDCL

RDDA

RSFT

ERROR

57K

TP

BE1

CORREC

ARI-ID

TA

BE0

0

0

0

0























1

1

0

0

























2

0

1

0































3

1

1

0

































4

0

0

1

























5

1

0

1































6

0

1

1































7

1

1

1

































 : open, ,  : Output enabled ( = reverse polarity)

Initial value : PT0 = 1, PT1 = 1, PT2 = 0 (Mode 3)

and RDS-ID pins changes to active high.

2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors

to output data.

Mode1 (PT2 = 0)

Pin T6 (TP)

TP = 0 detected

High (1)

TP = 1 detected

Low (0)

TP = Traffic program code