データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD1892JR データシート(PDF) 6 Page - Analog Devices

部品番号 AD1892JR
部品情報  Integrated Digital Receiver/Rate Converter
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD1892JR データシート(HTML) 6 Page - Analog Devices

Back Button AD1892JR Datasheet HTML 2Page - Analog Devices AD1892JR Datasheet HTML 3Page - Analog Devices AD1892JR Datasheet HTML 4Page - Analog Devices AD1892JR Datasheet HTML 5Page - Analog Devices AD1892JR Datasheet HTML 6Page - Analog Devices AD1892JR Datasheet HTML 7Page - Analog Devices AD1892JR Datasheet HTML 8Page - Analog Devices AD1892JR Datasheet HTML 9Page - Analog Devices AD1892JR Datasheet HTML 10Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 24 page
background image
AD1892
–6–
REV. 0
Subframe Status Outputs
Pin Name SOIC
I/O
Description
NOSIG
12
O
NOSIG (No Signal) is asserted HI when no biphase-mark input is applied to the AD1892 when
either the input sample rate is too high for the applied master clock (MCLK) frequency or, equiva-
lently, the master clock frequency is too low for the applied input sample rate. NOSIG is deasserted
LO during normal operation. This signal is asynchronous and has no particular timing relationship
with any of the clock signals associated with the AD1892.
ERROR
11
O
The ERROR pin is asserted HI when either a subframe parity error or a subframe validity error
occurs. Logically, ERROR = PARITY ERROR or VALIDITY ERROR. The ERROR pin is deas-
serted LO when neither parity nor validity errors are detected. The state of this output pin is not
directly reflected in the AD1892 status registers; rather, Status Register 0 has separate bits that
indicate parity and validity errors. The ERROR output should be clocked using the SFCLK signal
(Pin 8). The ERROR output signal is NOT sticky, so it can be used in applications that do not in-
clude a supporting microcontroller.
INT
10
O
INT (Interrupt) is asserted HI when any of the first 32 bits of Channel Status information changes
from block to block or when the Q-Channel subcode track number (Q10 through Q17) changes
from block to block (valid in consumer mode only). The Channel Status block spans 192 frames (or
subframes, since either the left or right channel C bit is stored), and the Q-Channel subcode block
spans 1176 subframes. INT is deasserted LO when neither the first 32 bits of Channel Status
changes from block to block when the Q-Channel subcode track number changes from block to
block. This output is mirrored in a status bit (Status Register 0, Bit 5). The INT output can be
clocked using the SFCLK signal (Pin 8). The INT output signal is sticky and can only be cleared by
reading Status Register 0.
U/CBIT
9
O
U/CBIT is either the subframe user bit or the Channel Status bit from the biphase-mark stream, fed
out serially, valid on the rising edge of the SFCLK signal (Pin 8). The choice between user bit and
Channel Status bit is determined by Bit 1 in Control Register 0 (0 user bit [default], 1 = Channel
Status bit). Changes at the subframe rate (two times the incoming sample rate.) See Figure 39 for
timing.
SFCLK
8
O
This SFCLK signal is used to clock the ERROR, INT and U/CBIT output status signals. Active
LO (rising edge active); see Figure 39 for timing. It is a LO pulse at the subframe rate (two times
the sample rate). The pulsewidth is approximately 1/64th of the incoming sample (frame) period.
Q-Channel Subcode Clock Output Signal
Pin Name SOIC
I/O
Description
QDFS
6
O
QDFS (Q-Channel Data Frame Sync) is a framing pulse indicating if the AD1892 has finished col-
lecting a full Q-Channel subcode block of user bits, which has a period of 1176 subframes. Can be
used as an interrupt signal to a microcontroller. The QDFS output is HI for one subframe period.
The QDFS frequency is 75 Hz when the incoming input sample rate is 44.1 kHz. See Figure 40 for
timing information.
Serial Control Port Signals
Pin Name SOIC
I/O
Description
CS
3
I
Chip Select/Latch signal for the serial control port. This input must be LO for any write or read
operation using the serial control port to be valid. This input should be tied HI when using the
AD1892 in a stand-alone (no external microcontroller) application. See the Serial Control Port
Timing in Figure 37 and the text below for more information.
CCLK
2
I
Serial Control Port Clock. This rising edge active input samples the address and data associated
with the serial control port. The frequency of CCLK signal must not exceed 1/8 the frequency of
the MCLK (Pin 28) signal. See the Serial Control Port Timing in Figure 37 and the text below for
more information.
SDI
4
I
Serial Data Input. This input signal is used to convey the serial 6-bit address, the read/
write indication
and the 8-bit write data for the AD1892 serial control port. See the Serial Control Port Timing in
Figure 37 and the text below for more information.
SDO
5
O
Serial Data Output. This three-state output is used to convey the serial 8-bit read data for the
AD1892 serial control port. It is a three-state output to allow multiple AD1892s to coexist on the same
SPI serial bus. See the Serial Control Port Timing in Figure 37 and the text below for more information.


同様の部品番号 - AD1892JR

メーカー部品番号データシート部品情報
logo
Analog Devices
AD1890 AD-AD1890 Datasheet
416Kb / 20P
   SamplePort Stereo Asynchronous Sample Rate Converters
REV. 0
AD1890JN AD-AD1890JN Datasheet
416Kb / 20P
   SamplePort Stereo Asynchronous Sample Rate Converters
REV. 0
AD1890JP AD-AD1890JP Datasheet
416Kb / 20P
   SamplePort Stereo Asynchronous Sample Rate Converters
REV. 0
AD1890 AD-AD1890_15 Datasheet
419Kb / 20P
   SamplePort Stereo Asynchronous Sample Rate Converters
REV. 0
AD1891 AD-AD1891 Datasheet
416Kb / 20P
   SamplePort Stereo Asynchronous Sample Rate Converters
REV. 0
More results

同様の説明 - AD1892JR

メーカー部品番号データシート部品情報
logo
Cirrus Logic
CS8422 CIRRUS-CS8422_09 Datasheet
734Kb / 82P
   24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver
logo
Texas Instruments
SRC4392 TI1-SRC4392_14 Datasheet
1Mb / 94P
[Old version datasheet]   Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter
logo
Cirrus Logic
CS8422 CIRRUS-CS8422_10 Datasheet
995Kb / 82P
   24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver
logo
Burr-Brown (TI)
SRC4382 BURR-BROWN-SRC4382 Datasheet
7Mb / 81P
   Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter
logo
Texas Instruments
SRC4382 TI1-SRC4382_14 Datasheet
1Mb / 84P
[Old version datasheet]   Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter
logo
Burr-Brown (TI)
SRC4392 BURR-BROWN-SRC4392 Datasheet
6Mb / 79P
   Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter
logo
Asahi Kasei Microsystem...
AKD4127-A AKM-AKD4127-A Datasheet
221Kb / 20P
   digital sample rate converter.
AKD4125-A AKM-AKD4125-A Datasheet
206Kb / 20P
   digital sample rate converter.
AKD4126-A AKM-AKD4126-A Datasheet
908Kb / 29P
   digital sample rate converter.
logo
Cirrus Logic
CS8420 CIRRUS-CS8420_07 Datasheet
1Mb / 94P
   DIGITAL AUDIO SAMPLE RATE CONVERTER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com