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AD1893JST データシート(PDF) 10 Page - Analog Devices

部品番号 AD1893JST
部品情報  Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD1893JST データシート(HTML) 10 Page - Analog Devices

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AD1893
–10–
REV. A
AB
OUTPUT SEQUENCE
PAST
FUTURE
AMPLITUDE
AMPLITUDE
SHORT
DELAY
LONG
DELAY
SMALL
OFFSET
LARGE
OFFSET
OFFSET INTO DENSE FIR FILTER COEFFICIENT ARRAY
TO ACCESS REQUIRED POLYPHASE FILTER
REQUIRED FILTER GROUP DELAY TO
COMPUTE REQUESTED OUTPUT SAMPLE
INPUT SEQUENCE
Figure 5. Input and Output Clock Event Relationship
A short delay corresponds to a large offset into the dense FIR
filter coefficient array, and a long delay corresponds to a small
offset. Note that because the output sample clock can arrive at
any arbitrary time with respect to the input sample clock, the
selection of a polyphase filter with which to convolve the input
sequence occurs on every output sample clock event. Occasion-
ally the FIFO which holds the input sequence in the FIR con-
volver is either not incremented, or incremented by two between
output sample clocks (see periods A and B in Figure 5); this
happens more often when the input and output sample clock
frequencies are dissimilar than when they are close together.
However, in this situation, an appropriate polyphase filter is
selected to process the input signal, and thus an accurate output
sample is computed. Input and output samples are not skipped
or repeated (unless the input FIFO underflows or overflows), as
is the case in some other sample rate converter implementations.
To obtain an accurate conversion, a large number of polyphase
filters are needed. The AD1893 SamplePort uses the equivalent
of 65,536 polyphase filters to achieve its high quality distortion
and dynamic range specifications.
Sample Clock Tracking
It should be clear that, in either model, the correct computation
of the ratio between the input sample rate (as determined from
the left/right input clock, LR_I) and the output sample rate (as
determined from the left/right output clock, LR_O) is critical to
the quality of the output data stream. It is straightforward to
compute this ratio if the sample rates are fixed and synchronous;
the challenge is to accurately track dynamically varying and
asynchronous sample rates, as well as to account for jitter.
The AD1893 SamplePort solves this problem by embedding the
ratio computation circuit within a digital servo control loop, as
shown in Figure 6. This control loop includes special provisions
to allow for the accurate tracking of dynamically changing
sample rates. The outputs of the control loop are the starting
read addresses for the input data FIFO and the filter coefficient
ROM. These start addresses are used by the FIFO and ROM
address generators, as shown in Figure 6.
The input data FIFO write address is generated by a counter
which is clocked by the input sample clock (i.e., LR_I). It is very
important that the FIFO read address and the FIFO write ad-
dress do not cross, as this means that the FIFO has either
underflowed or overflowed. This consideration affects the
choice of settling time of the control loop. When a step change
in the sample rate occurs, the relative positions of the read and
write addresses will change while the loop is settling. A fast
settling loop will act to keep the FIFO read and write addresses
separated better than a slow settling loop. The AD1893 includes
a user selectable pin (SETLSLW) to set the loop settling time
that essentially changes the coefficients of the digital servo con-
trol loop filter. The state of the SETLSLW pin can be changed
on-the-fly but is normally set and forgotten.
FIFO WRITE
ADDRESS
GENERATOR
FIFO
SERIAL DATA
INPUT UNIT
FIFO READ
ADDRESS
GENERATOR
ACCUMULATOR
SERIAL DATA
OUTPUT UNIT
SAMPLE CLOCK RATIO
SERVO CONTROL LOOP
POLYPHASE
COEFFICIENT
ROM
ROM ADDRESS
GENERATOR
POLYPHASE FILTER
SELECTOR
DATA_I
L
R_I
L
R_O
WCLK_O
BCLK_O
WCLK_I
BCLK_I
FIR CONVOLVER
DATA_O
START
ADDRESS
FREQUENCY
RESPONSE
COMPRESSION
FSOUT < FSIN
L
R_I
(FSIN)
L
R_O
(FSOUT)
L
R_I
L
R_I
L
R_O
Figure 6. Functional Block Diagram


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