AD2S90

REV. D

–6–

ABSOLUTE POSITION OUTPUT

SERIAL INTERFACE

Absolute angular position is represented by serial binary data

and is extracted via a three-wire interface, DATA,

CS and

SCLK. The DATA output is held in a high impedance state

when

CS is HI.

Upon the application of a Logic LO to the

CS pin, the DATA

output is enabled and the current angular information is trans-

ferred from the counters to the serial interface. Data is retrieved

by applying an external clock to the SCLK pin. The maximum

data rate of the SCLK is 2 MHz. To ensure secure data retrieval

it is important to note that SCLK should not be applied until a

minimum period of 600 ns after the application of a Logic LO

to

CS. Data is then clocked out, MSB first, on successive nega-

tive edges of the SCLK; 12 clock edges are required to extract

the full 12 bits of data. Subsequent negative edges greater than

the defined resolution of the converter will clock zeros from the

data output if

CS remains in a low state.

If a resolution of less than 12 bits is required, the data access

can be terminated by releasing

CS after the required number of

bits have been read.

LSB

MSB

t*

CSB

SCLK

DATA

Figure 6. Serial Read Cycle

CS can be released a minimum of 100 ns after the last negative

edge. If the user is reading data continuously,

CS can be reap-

plied a minimum of 250 ns after it is released (see Figure 6).

The maximum read time is given by: (12-bits read @ 2 MHz)

Max RD Time = [600 + (12

× 500) + 600 + 100] = 7.30 µs.

INCREMENTAL ENCODER OUTPUTS

The incremental encoder emulation outputs A, B and NM are

free running and are always valid, providing that valid resolver

format input signals are applied to the converter.

The AD2S90 emulates a 1024-line encoder. Relating this to

converter resolution means one revolution produces 1024 A, B

pulses. B leads A for increasing angular rotation (i.e., clockwise

direction). The addition of the DIR output negates the need for

external A and B direction decode logic. DIR is HI for increas-

ing angular rotation.

The north marker pulse is generated as the absolute angular

position passes through zero. The AD2S90 supports the three

industry standard widths controlled using the NMC pin. Figure

7 details the relationship between A, B and NM. The width of

NM is defined relative to the A cycle.

A

B

90

180

NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE

360

SELECTABLE WITH THREE - LEVEL

CONTROL PIN "MARKER" DEFAULT

TO 90 USING INTERNAL PULL - UP.

*

WIDTH

LEVEL

90

180

360

0

INCREASING ANGLE

Figure 7. A, B and NM Timing

Unlike incremental encoders, the AD2S90 encoder output is

not subject to error specifications such as cycle error, eccentric-

ity, pulse and state width errors, count density and phase

φ.

The maximum speed rating, n, of an encoder is calculated from

revolution).

n

=

60

× f

MAX

PPR

The AD2S90 A, B pulses are initiated from CLKOUT which

has a maximum frequency of 2.048 MHz. The equivalent

encoder switching frequency is:

1/4

× 2.048 MHz = 512 kHz (4 updates = 1 pulse)

At 12 bits the ppr = 1024, therefore the maximum speed, n, of

the AD2S90 is:

n

rpm

=

×

=

60

512000

1024

30000

is specified from 20 kHz (photo diodes) to 125 kHz (laser based)

depending on the light system used. A 1024 line laser-based

encoder will have a maximum speed of 7300 rpm.

The inclusion of A, B outputs allows the AD2S90 + resolver

solution to replace optical encoders directly without the need to

change or upgrade existing application software.