–7–

REV. A

AD2S93

Calculation of the component values for the bandwidth is de-

tailed below. For more detailed information on component

value selection for the AD2S93, please consult the “Passive

Component Selection and Dynamic Modeling Software for the

AD2S93 LVDT-to-Digital Converter.”

VCO Gain G (1) Mode 1

The available bandwidth with this option is from 0.5 kHz to

1.25 kHz.

C1 = 1/(800

C2 = 8

× C1

R2 = 45

× Fo

3 dB point.

VCO Gain G (2) Mode 2

The available bandwidth with this option is from 45 Hz

to 500 Hz.

C1 = 1/(2400

C2 = 8 C1

R2 = 45

× Fo

3 dB point.

INTERFACING TO THE AD2S93 (SEE “TIMING

CHARACTERISTICS”)

The absolute position information is extracted via a three-wire

interface, DATA, CS and SCLK. The DATA output is held in

a high impedance state when CS is high.

Upon the application of logic low to the CS pin, the DATA is

enabled and the current position information is transferred from

the counters to the serial interface. Data is retrieved by applying

an external clock to the SCLK pin. The maximum data rate of

the SCLK is 2 MHz. To ensure secure data retrieval, it is

important to note that SCLK should not be applied until a

minimum period of 600 ns after the application of logic low to

CS

. Data is then clocked out on successive positive edges of

SCLK: 16 clock edges are required to extract the entire data

word. Subsequent positive edges greater than the defined reso-

lution of the converter will clock zeros from the data output if

CS

remains in a low state. The format of the data read is shown

in Table I.

Table I.

DB0

DB1

DB2

DB3

DATA DB4–D15

MSB LSB

Function

LOS

OVR

UNR

SIGN

MAGNITUDE

If less than the full 16-bit word is required, then the data read

can be terminated by releasing CS after the required number of

bits have been read.

CS

can be released a minimum of 100 ns after the last positive

edge. If the user is reading data continuously, CS can be reap-

plied after a minimum of 600 ns after it is released. The mini-

mum repetitive read time of the same converter is given by (16

bits read @ 2 MHz). Min RD Time = [600 + (16

× 500) +

600] = 9.2

µs.

IN-BUILT DIAGNOSTICS

The first three bits read from the serial interface preceding the

sign and magnitude data can be used to determine whether the

data is valid or not. Over and underrange (OVR, UNR) denote

the two extremes of the LVDT stroke where linearity of the

LVDT may degrade. Loss of signal LOS is an open drain out-

put which pulls high (12 k

Ω pull up) when one of the following

conditions is satisfied:

1. A and/or B is disconnected.

2. REF is disconnected.

Note: LOS has a response time of 50 ms max to the conditions

stated above, see “Specifications.”

CONNECTING THE CONVERTER

to Pin 16. Reversal of these power supplies will destroy this device.

For LVDT connections to the converter please refer to Figures

5 through 7. On all connections, the maximum input reference

operating range, A–B should not exceed 1.0 V rms

± 10%. The

AD2S93 AGND point is the point at which all analog signal

grounds should be connected. Ground returns from the LVDT

should be connected to AGND. The AD2S93 DGND pin

should be connected to the AD2S93 AGND pin. Ancillary Digi-

tal circuitry must be connected to the Star Point and not to the

AD2S93 AGND pin.

In all cases, the AD2S93 has been configured with the following

dynamics.

Reference Frequency

5 kHz

3 dB Bandwidth

625 Hz

Vco Gain is set in MODE 1 where VCO GAIN is connected to

VEL.

Using the procedure described in “setting the converter band-

width” the following preferred values (E12 series) were calcu-

lated:

C1 = 3.3 nF

C2 = 27 nF

R2 = 27 k

Ω

CALCULATING HF FILTER (C3, C4, R5, R6)

15 k

Ω ≤ R5 = R6 ≤ 56 kΩ

C 3 =C4 =

1

2

π R5 F

REF

So, C3 = 1 nF, R5 = R6 = 33 k

Ω, C4 = 1 nF and in all cases

R7 = 15 k

Ω.

Half-Bridge Type LVDT Connection

In this method of connection, it is necessary to add two addi-

a reference for the AD2S93. In selecting the bridge completion

ing used for differential measurements, the resistors can be re-

placed by the second LVDT.