AD5582YRU-REEL7 datasheet(2/8 Pages) AD

部品番号	AD5582YRU-REEL7

部品情報	QUAD, Parallel-Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converter

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PRELIMINARY TECHNICAL DATA

AD5582/AD5583

This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future

manufacture unless otherwise agreed to in writing.

REV PrC, 23 APR '01

2

ELECTRICAL CHARACTERISTICS at VDD =+5V, VSS = -5V, VL = +5V±10%, VREFH = +2.5V, VREFL = -2.5V, -40°C < TA < +125°C, unless otherwise noted.

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution

1

N

AD5582

12

Bits

Resolution

1

N

AD5583

10

Bits

Relative Accuracy

2

INL

-1

+1

LSB

Differential Nonlinearity

2

DNL

Monotonic

-1

LSB

Zero-Scale Error

VZSE

Data = 000H

2

LSB

Full-Scale Voltage Error

VFSE

Data = FFFH

2

LSB

Full-Scale Tempco

3

TCVFS

10

ppm/

oC

REFERENCE INPUT

VREFH Input Range

4

VREFH

VSS

V

DD

V

VREFL Input Range

4

VREFL

VSS

V

DD

V

Input Resistance

8

RREF

Data = 555H

10

K

Ω5

Input Capacitance

3

CREF

80

pF

REF Input Current

IREF

500

µA

REF Multiplying Bandwidth

BWREF

Hz

ANALOG OUTPUT

Output Current

IOUT

Data = 800H, ∆VOUT = 4LSB

±2

mA

Capacitive Load

3

CL

No Oscillation

500

pF

LOGIC INPUTS

Logic Input Low Voltage

VIL

VL = 5V ± 10%

0.8

V

Logic Input High Voltage

VIH

VL = 5V ± 10%

2.4

V

Input Leakage Current

IIL

µA

Input Capacitance

3

CIL

pF

Output Voltage High

VOH

IOH = -0.8mA

2.4

V

Output Voltage Low

VOL

IOL = 1.6mA

0.4

V

AC CHARACTERISTICS

Output Slew Rate

SR

Data = 000H to FFFH to 000H

2

V/

µs

Settling Time

7

tS

To ±0.1% of Full Scale

5

µs

Shutdown Recovery

tSDR

µs

DAC Glitch

Q

Code 7FFH to 800H to 7FFH

100

nVs

Digital Feed Through

VOUT/tCS

Data=800H, CS toggles at f=16MHz

5

nVs

Analog Crosstalk

VOUT/VREF

VREF = 1.5VDC +1VP-P, Data = 000H, f=100KHz

-80

dB

Output Noise

eN

40

nV

√Hz

SUPPLY CHARACTERISTICS

Positive Supply Current

IDD

VIL = 0V, No Load

3

mA

Negative Supply Current

ISS

VIL = 0V, No Load

3

mA

Power Dissipation

PDISS

VIL = 0V, No Load

30

mW

Power Supply Sensitivity

PSS

∆VDD = ±5%

30

ppm/V

NOTES:

1.

DAC Output Equation: VOUT = VREFL + [(VREFH-VREFL)*Code/2^N], where Code = data loaded in corresponding DAC register A, B, C, D and N equals the

DAC resolution AD5582 = 12, AD5583 = 10 bits. One LSB = VREF/4096V for the 12-bit AD5582.

2.

The first two codes (000H, 001H) are excluded from the linearity error measurement in single supply operation.

3.

These parameters are guaranteed by design and not subject to production testing.

4.

When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage

minus the offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the operation section of the data

sheet.

5.

Typical specifications represent average readings measured at 25°C.

6.

The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground in single supply operation.

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