データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD6620S データシート(PDF) 17 Page - Analog Devices

部品番号 AD6620S
部品情報  65 MSPS Digital Receive Signal Processor
Download  43 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD6620S データシート(HTML) 17 Page - Analog Devices

Back Button AD6620S Datasheet HTML 13Page - Analog Devices AD6620S Datasheet HTML 14Page - Analog Devices AD6620S Datasheet HTML 15Page - Analog Devices AD6620S Datasheet HTML 16Page - Analog Devices AD6620S Datasheet HTML 17Page - Analog Devices AD6620S Datasheet HTML 18Page - Analog Devices AD6620S Datasheet HTML 19Page - Analog Devices AD6620S Datasheet HTML 20Page - Analog Devices AD6620S Datasheet HTML 21Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 17 / 43 page
background image
AD6620
–17–
REV. 0
Diversity Channel Real Mode
In the Diversity Channel Real mode the A/B pin serves not only
as an input enable but also to determine which channel is being
sampled on a given CLK edge. A high on the A/B pin marks
channel A data and a low on A/B marks channel B data. The
AD6620 only accepts the first sample after an A/B transition.
All subsequent samples are disregarded until A/B changes again.
When full rate input timing is employed in the Diversity Chan-
nel Real mode, A/B must toggle on every edge of CLK for new
data to be clocked into the AD6620.
tSI
tHI
CLK
IN[15:0]
EXP[2:0]
A/B
AN
BN
BN+1
AN+1
AN+2
BN+2
Figure 30. Full Rate Input Timing, Diversity Channel Real
Mode
If fractional rate input timing is necessary in the Diversity Chan-
nel Real Mode, the A/B pin must toggle at half the rate of the
A/D sample clock. The timing diagram below shows a 3
× pro-
cessing clock. In this situation there will be one ADC encode
pulse for every three AD6620 CLK pulses and data must be
taken on every third CLK pulse. The CLK edges that corre-
spond to the latching of A and B channel data are shown in
Figure 31.
AN
tSI
tHI
CLK
IN[15:0]
EXP[2:0]
A/B
BN
Figure 31. Fractional Rate Input Timing (3
× CLK), Diversity
Channel Real Mode
Single Channel Complex Mode
In the Single Channel Complex input mode, A/B high identi-
fies the in-phase samples and A/B low identifies quadrature
samples. The quadrature samples are paired with the previous
in-phase samples. The timing for this mode is the same as that
of the Diversity Channel Real Mode. This mode is useful for
accepting complex output data from another AD6620 or an-
other source to increase filtering and or decimation rates.
In the Single Channel Complex Mode the CIC2 decimation
must be set to two (MCIC2 = 2). This is necessary in order to
allow enough CLK cycles to process the complex input data as
described below.
First clock cycle: (A/B high).
– I data loaded from the input port.
– The I data-path gets I
× cosine.
– The Q data-path gets I
× sine.
– The first integrator of the CIC2 adds these values to its
previous sums.
– The rest of the CIC2 is idle.
Second clock cycle: (A/B low).
– Q data loaded from the input port.
– The I data-path gets Q
× sine.
– The Q data-path gets Q
× cosine.
– The first integrator of the I path of the CIC2 completes the
sum (I
× cosine - Q × sine) and the first integrator of the Q
path of the CIC2 completes the sum j(I
× sine + Q × cosine).
– The rest of the CIC2 operates on these sums, which is the
complete complex multiply. The data is then multiplexed
through the rest of the chip as if it were single channel real data.


同様の部品番号 - AD6620S

メーカー部品番号データシート部品情報
logo
Analog Devices
AD6620S/PCB AD-AD6620S/PCB Datasheet
399Kb / 44P
   67 MSPS Digital Receive Signal Processor
REV. A
AD6620S/PCB AD-AD6620S/PCB Datasheet
374Kb / 44P
   67 MSPS Digital Receive Signal Processor
REV. A
More results

同様の説明 - AD6620S

メーカー部品番号データシート部品情報
logo
Analog Devices
AD6620ASZ AD-AD6620ASZ Datasheet
374Kb / 44P
   67 MSPS Digital Receive Signal Processor
REV. A
AD6620 AD-AD6620_15 Datasheet
399Kb / 44P
   67 MSPS Digital Receive Signal Processor
REV. A
AD6620AS AD-AD6620AS Datasheet
399Kb / 44P
   67 MSPS Digital Receive Signal Processor
REV. A
AD6624 AD-AD6624_15 Datasheet
566Kb / 40P
   Four-Channel, 80 MSPS Digital Receive Signal Processor
REV. B
AD6624A AD-AD6624A_15 Datasheet
642Kb / 40P
   Four-Channel, 100 MSPS Digital Receive Signal Processor
REV. 0
AD6624 AD-AD6624 Datasheet
509Kb / 40P
   Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP)
REV. B
AD6624A AD-AD6624A Datasheet
636Kb / 40P
   Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
REV. 0
AD6634 AD-AD6634_15 Datasheet
931Kb / 52P
   80 MSPS, Dual-Channel WCDMA Receive Signal Processor
REV. 0
AD6635 AD-AD6635_15 Datasheet
805Kb / 60P
   4-Channel, 80 MSPS WCDMA Receive Signal Processor
REV. 0
AD6634 AD-AD6634 Datasheet
925Kb / 52P
   80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP)
REV. 0
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com