AD7339

–10–

REV. 0

The 4-bit offset nulling feature has a LSB size of 7.6 mV; thereby,

allowing the user to vary the DAC output by

±115 mV.

Table I. Writing to the Parallel DACs Offset Registers

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Address

X

X

Factory/

Decr/

Data Word

User Offset

Incr

The DACs use offset binary coding with 1 LSB = FS/256 =

2.8/256 = 10.94 mV. Table II shows the ideal input code to

output voltage relationship.

Table II. Ideal Input/Output Code Table

DAC Latch Contents

MSB

LSB

000 0000 0

–1.4 V

000 0000 1

–1.38906 V

011 1111 1

–0.01094 V

100 0000 0

0 V

100 0000 1

+0.01094 V

111 1111 0

+1.37812 V

111 1111 1

+1.38906 V

± 1.4 V.

Serial DACs

The AD7339 has two serial DACs on board. The serial DACs

have an architecture similar to the parallel DACs. The 8-bit

digital word to each DAC is serially loaded. The serial DACs

have a common serial port. To distinguish between the two

DACs, 10-bit bursts are transferred to the DACs, the two MSBs

identifying the DAC to which the 8-bit word is to be loaded.

Table III shows the truth table for the two MSBs.

The serial word is loaded into the serial register using SDATA

and SCLK. SCLK is a gated clock of nominal value 256 kHz,

which should be active only when the 10-bit word is being

loaded into the register; i.e., SCLK should consist of 10 pulses.

If SCLK is continuous, or if it consists of more than 10 pulses,

the data shifted into the serial register will be shifted out of the

serial register so the register will not contain valid data. When

the serial register is not being written to, SCLK should idle low.

The serial data bits are read into the serial register on the rising

edge of SCLK, the two MSBs of the word identifying the DAC

to which the word is being written, and the eight LSBs of the

10-bit word containing the 8-bit word to be converted, the 8-bit

word being transferred MSB first. SDATA idles low.

Table III. Serial DACs Truth Table

D9

D8

DAC to be Written to

0

0

DAC A Offset Register Is Loaded

0

1

DAC 1 Register Is Loaded

1

0

DAC 0 Register Is Loaded

1

1

DAC B Offset Register Is Loaded

The 8-bit word is loaded into the DAC from the register using

LATCH. Data is loaded into the DACs on the falling edge of

LATCH. When the D-to-A conversion is performed, the analog

output is altered accordingly. The analog output will remain

valid until the next falling edge of LATCH, at which stage the

next digital word in the register is converted. LATCH is nor-

mally low, the input being pulsed to load the DACs, the DACs

being loaded on the falling edge of LATCH.

The analog output is available on the SDAC0S/SDAC1S pin.

Each DAC has an analog output of 0.2 V to AVDD – 0.247 V,

an input of 00H generating an analog output of 0.2 V while a

digital input of FFH produces an analog output of AVDD –

0.247 V, i.e., the serial DACs use straight binary coding. The

analog output is generated by the on board reference. There-

when the digital word equals all 1s. However, when AVDD is

less than 5.247 V, the output is limited to 0.247 V below AVDD

as the amplifier clips the output.

The output from the current source is converted to a voltage

using an operational amplifier. The amplifier is configured to

gain the signal by two; however, the gain of the amplifier can be

adjusted by tying a resistor between SDAC0F/SDAC1F and

SDAC0S/SDAC1S. The resistors on board the AD7339 have a

value of 20 k

Ω.

Power-Down

Each section of the AD7339 can be individually powered down.

The ADC, parallel DACs and serial DACs have individual

power-down pins, which allows each section to be powered

down when it is not being used, thus minimizing the current

consumption of the AD7339.

Pin ADCPDB is used to place the ADC in sleep mode. When

this pin is taken low, the ADC is powered down. For normal

operation, ADCPDB is high.

When the parallel DACs are not being used, they can be placed

in power-down mode using DACPDB. When DACPDB is low,

both DACs are powered down. The reference outputs VREFA

and VREFB are also powered down. During power-down, the

analog outputs DACA and DACB, as well as the reference out-

puts, are pulled down to ground. When the DACs are powered up,

the analog outputs settle to the bias voltage VREFA/VREFB.

The serial DACs are powered down using SDACPDB. When

this pin is tied low, the serial DACs are placed in sleep mode.

When a converter is powered up, 100

µs are required for the

analog and digital circuitry to settle. Conversions can commence

when the circuitry has settled.

The reference on board the AD7339 is permanently powered

up. While the outputs VREFA and VREFB can be powered

down, the reference voltage, which is available on pin VREF, is

always available.