データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD7472ARU データシート(PDF) 6 Page - Analog Devices

部品番号 AD7472ARU
部品情報  1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
Download  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD7472ARU データシート(HTML) 6 Page - Analog Devices

Back Button AD7472ARU Datasheet HTML 2Page - Analog Devices AD7472ARU Datasheet HTML 3Page - Analog Devices AD7472ARU Datasheet HTML 4Page - Analog Devices AD7472ARU Datasheet HTML 5Page - Analog Devices AD7472ARU Datasheet HTML 6Page - Analog Devices AD7472ARU Datasheet HTML 7Page - Analog Devices AD7472ARU Datasheet HTML 8Page - Analog Devices AD7472ARU Datasheet HTML 9Page - Analog Devices AD7472ARU Datasheet HTML 10Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 16 page
background image
REV. A
AD7470/AD7472
–6–
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
CS
Chip Select. Active low logic input used in conjunction with
RD to access the conversion result. The conversion
result is placed on the data bus following the falling edge of both
CS and RD. CS and RD are both connected to
the same AND gate on the input so the signals are interchangeable.
CS can be hardwired permanently low.
RD
Read Input. Logic Input used in conjunction with
CS to access the conversion result. The conversion result is
placed on the data bus following the falling edge of both
CS and RD. CS and RD are both connected to same
AND gate on the input so the signals are interchangeable.
CS and RD can be hardwired permanently low in which
case, the data bus is always active and the result of the new conversion is clocked out slightly before to the BUSY
line going low.
CONVST
Conversion Start Input. Logic Input used to initiate conversion. The input track/hold amplifier goes from track
mode to hold mode on the falling edge of
CONVST and the conversion process is initiated at this point. The con-
version input can be as narrow as 15 ns. If the
CONVST input is kept low for the duration of conversion and is
still low at the end of conversion, the part will automatically enter sleep mode. If the part enters this sleep mode,
the next rising edge of
CONVST wakes up the part. Wake-up time for the part is typically 1
µs.
CLK IN
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7472 takes 14 clock cycles while conversion time for the AD7470 takes 12 clock cycles. The frequency of this
master clock input, therefore, determines the conversion time and achievable throughput rate. While the ADC is
not converting, the Clock-In pad is in three-state and thus no clock is going through the part.
BUSY
BUSY Output. Logic Output indicating the status of the conversion process. The BUSY signal goes high after the
falling edge of
CONVST and stays high for the duration of conversion. Once conversion is complete and the con-
version result is in the output register, the BUSY line returns low. The track/hold returns to track mode just prior
to the falling edge of BUSY and the acquisition time for the part begins when BUSY goes low. If the
CONVST
input is still low when BUSY goes low, the part automatically enters its sleep mode on the falling edge of BUSY.
REF IN
Reference Input. An external reference must be applied to this input. The voltage range for the external reference
is 2.5 V
±1% for specified performance.
AVDD
Analog Supply Voltage, +2.7 V to +5.25 V. This is the only supply voltage for all analog circuitry on the AD7470/
AD7472. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V
apart even on a transient basis. This supply should be decoupled to AGND.
DVDD
Digital Supply Voltage, +2.7 V to +5.25 V. This is the supply voltage for all digital circuitry on the AD7470/
AD7472 apart from the output drivers. The DVDD and AVDD voltages should ideally be at the same potential and
must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7470/AD7472. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis.
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7470 and AD7472. The
DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even
on a transient basis.
VIN
Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents a
high dc input impedance.
VDRIVE
Supply Voltage for the Output Drivers, +2.7 V to +5.25 V. This voltage determines the output high voltage for the
data output pins. It allows the AVDD and DVDD to operate at 5 V (and maximize the dynamic performance of the
ADC) while the digital outputs can interface to 3 V logic.
DB0–DB9/11
Data Bit 0 to Data Bit 9 (AD7470) and DB11 (AD7472). Parallel digital outputs that provide the conversion
result for the part. These are three-state outputs that are controlled by
CS and RD. The output high voltage level
for these outputs is determined by the VDRIVE input.


同様の部品番号 - AD7472ARU

メーカー部品番号データシート部品情報
logo
Analog Devices
AD7472ARU AD-AD7472ARU Datasheet
325Kb / 20P
   1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
REV. B
AD7472ARU AD-AD7472ARU Datasheet
325Kb / 20P
   1.75 MSPS, 4 mW 10-Bit-12-Bit Parallel ADCs
REV. B
AD7472ARU-REEL AD-AD7472ARU-REEL Datasheet
325Kb / 20P
   1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
REV. B
AD7472ARU-REEL AD-AD7472ARU-REEL Datasheet
325Kb / 20P
   1.75 MSPS, 4 mW 10-Bit-12-Bit Parallel ADCs
REV. B
AD7472ARU-REEL7 AD-AD7472ARU-REEL7 Datasheet
325Kb / 20P
   1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
REV. B
More results

同様の説明 - AD7472ARU

メーカー部品番号データシート部品情報
logo
Analog Devices
AD7472ARZ AD-AD7472ARZ Datasheet
325Kb / 20P
   1.75 MSPS, 4 mW 10-Bit-12-Bit Parallel ADCs
REV. B
AD7472 AD-AD7472_15 Datasheet
529Kb / 21P
   1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
REV. B
AD7470 AD-AD7470_15 Datasheet
529Kb / 21P
   1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
REV. B
AD7470 AD-AD7470_03 Datasheet
325Kb / 20P
   1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
REV. B
AD7934BRUZ-REEL7 AD-AD7934BRUZ-REEL7 Datasheet
768Kb / 32P
   4-Channel, 1.5 MSPS, 10-Bit and 12-Bit Parallel ADCs with a Sequencer
REV. B
AD7933 AD-AD7933_15 Datasheet
768Kb / 32P
   4-Channel, 1.5 MSPS, 10-Bit and 12-Bit Parallel ADCs with a Sequencer
REV. B
AD7933 AD-AD7933 Datasheet
1Mb / 32P
   4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
Rev.PrG
AD7934 AD-AD7934_15 Datasheet
768Kb / 32P
   4-Channel, 1.5 MSPS, 10-Bit and 12-Bit Parallel ADCs with a Sequencer
REV. B
AD7475 AD-AD7475_V01 Datasheet
519Kb / 24P
   1 MSPS,12-Bit ADCs
Rev. D
AD7475 AD-AD7475 Datasheet
218Kb / 16P
   1 MSPS, 12-Bit ADCs
REV. A
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com