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AD7777 データシート(PDF) 9 Page - Analog Devices |
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AD7777 データシート(HTML) 9 Page - Analog Devices |
9 / 12 page AD7776/AD7777/AD7778 –9– REV. 0 Table I. AD7776/AD7777/AD7778 Truth Table for Microprocessor Interfacing CS RD WR DB0–DB9 Function/Comments 1 X* X* High Z Data Port High Impedance 01 j CR Data Load control register (CR) data to control register and start a conversion. 0 k 1 ADC Data ADC data placed on data bus. Depending upon location CR6 of the control register, one or two Read instructions will be required. If CR6 is low, i.e., single channel conversion selected, a read instruction returns the contents of ADCREG1. Succeeding read instructions continue to return the contents of ADCREG1. If CR6 is high, i.e., simultaneous sampling (double conversion) selected, the first read instruction returns the contents of ADCREG1 while the second read instruction returns the contents of ADCREG2. A third read instruction returns ADCREG1 again, the fourth ADCREG2, etc. *X = Don’t Care DESIGN INFORMATION Layout Hints Ensure that the layout for the printed circuit board has the digi- tal and analog grounds separated as much as possible. Take care not to run any digital track alongside an analog signal track. Guard (screen) the analog input(s) with RTN. Establish a single point analog ground separate from the logic system ground and as close as possible to the AD7776/AD7777/ AD7778. Both the RTN and AGND pins on the AD7776/ AD7777/AD7778 and all other signal grounds should be con- nected to this single point analog ground. In turn, this star ground should be connected to the digital ground at one point only—preferably at the low impedance power supply itself. Low impedance analog and digital power supply common re- turns are important for correct operation of the devices, so make the foil width for these tracks as wide as possible. In order to ensure a low impedance +5 V power supply at the actual VCC pin, it will be necessary to employ bypass capacitors from the pin itself to DGND. A 4.7 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor is sufficient. ADC Corruption Executing a read instruction to the AD7776/AD7777/AD7778 while a conversion is in progress will immediately halt the con- version and return invalid data over the data bus. The BUSY/ INT output pin should be monitored closely and all read in- structions to the AD7776/AD7777/AD7778 prevented while this output shows that a conversion is in progress. Executing a write instruction to the AD7776/AD7777/AD7778 while a conversion is in progress immediately halts the conver- sion, the falling edge of WR driving the BUSY/INT output high. The analog input(s) is sampled as normal and a new conversion sequence (dependent upon CR6) is started. ADC Conversion Time Although each conversion takes only 14 CLKIN cycles, it can take between 4.5 to 5.5 CLKIN cycles to acquire the analog input(s) after the WR input goes high and before any conver- sions start. TERMINOLOGY Relative Accuracy For the AD7776, AD7777 and AD7778, relative accuracy or endpoint nonlinearity is the maximum deviation, in LSBs, of the ADC’s actual code transition points from a straight line drawn between the endpoints of the ADC transfer function. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified maximum differential nonlinearity of ±1 LSB ensures no missed codes. Bias Offset Error For an ideal 10-bit ADC, the output code for an input voltage equal to VBIAS should be midscale. The bias offset error is the difference between the actual midpoint voltage for midscale code and VBIAS, expressed in LSBs. Bias Offset Error Match This is a measure of how closely the bias offset errors of all channels track each other. The bias offset error match of any channel must be no further away than 10 LSBs from the bias offset error of any other channel, regardless of whether the channels are independently sampled or simultaneously sampled. Plus and Minus Full-Scale Error The input channels of the ADC can be considered to have bipolar (positive and negative) input ranges, but which are re- ferred to VBIAS (or REFIN) instead of AGND. Positive full-scale error for the ADC is the difference between the actual input voltage required to produce the plus full-scale code transition and the ideal input voltage (VBIAS + VSWING –1.5 LSB), ex- pressed in LSBs. Minus full-scale error is similarly specified for the minus full-scale code transition, relative to the ideal input voltage for this transition (VBIAS – VSWING + 0.5 LSB). Note that the full-scale errors for the ADC input channels are measured after their respective bias offset errors have been adjusted out. Plus and Minus Full-Scale Error Match This is a measure of how closely the full-scale errors of all chan- nels track each other. The full-scale error match of any channel must be no further away than 10 LSBs from the respective full- scale error of any other channel, regardless of whether the chan- nels are independently sampled or simultaneously sampled. |
同様の部品番号 - AD7777 |
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同様の説明 - AD7777 |
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