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データシートサーチシステム |
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データシートサーチシステム |
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AD7835 データシート(PDF) 3 Page - Analog Devices |
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AD7835 データシート(HTML) 3 Page - Analog Devices |
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3 / 16 page  AD7834/AD7835 REV. A –3– TIMING SPECIFICATIONS1 Parameter Limit at TMIN, TMAX Units Description AD7834 Specific t1 2 100 ns min SCLK Cycle Time t2 2 50 ns min SCLK Low Time @ +25 °C 60 ns min SCLK Low Time –40 °C to +85°C 66 ns min SCLK Low Time –55 °C to +125°C t3 2 30 ns min SCLK High Time t4 30 ns min FSYNC , PAEN Setup Time t5 40 ns min FSYNC , PAEN Hold Time t6 30 ns min Data Setup Time t7 10 ns min Data Hold Time t8 0 ns min LDAC to FSYNC Setup Time t9 40 ns min LDAC to FSYNC Hold Time t21 20 ns min Delay Between Write Operations AD7835 Specific t11 15 ns min A0, A1, A2, BYSHF to CS Setup Time t12 15 ns min A0, A1, A2, BYSHF to CS Hold Time t13 0 ns min CS to WR Setup Time t14 0 ns min CS to WR Hold Time t15 40 ns min WR Pulse Width t16 40 ns min Data Setup Time t17 10 ns min Data Hold Time t18 0 ns min LDAC to CS Setup Time t19 0 ns min CS to LDAC Setup Time t20 0 ns min LDAC to CS Hold Time General t10 40 ns min LDAC , CLR Pulse Width NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2Rise and fall times should be no longer than 50 ns. Specifications subject to change without notice. (VCC = +5 V ± 5%; V DD = +15 V ± 5%; V SS = –15 V ± 5%; AGND = DGND = 0 V) t12 t14 t17 t16 t15 t10 t18 t19 t11 t13 A0. A1 A2 BYSHF CS WR DATA LDAC (SIMULTANEOUS UPDATE) LDAC (PRE-CHANNEL UPDATE) Figure 2. AD7835 Timing Diagram t1 t3 t10 t20 t9 t4 LDAC (SIMULTANEOUS UPDATE) LDAC (PRE-CHANNEL UPDATE) 1ST CLK 2ND CLK 24TH CLK t5 t8 t2 D0 D1 t7 t6 D22 D23 SCLK DIN FSYNC Figure 1. AD7834 Timing Diagram |
同様の部品番号 - AD7835 |
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同様の説明 - AD7835 |
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