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AD7834AR データシート(PDF) 9 Page - Analog Devices |
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AD7834AR データシート(HTML) 9 Page - Analog Devices |
9 / 16 page AD7834/AD7835 REV. A –9– Table I. D23 Control D23 Control Function 0 Ignore following 23 bits of information. 1 Use following 23 bits of address and data as normal. D22 and D21: Decoded to select one of the four DAC channels within a device. The truth table for D22 and D21 is as shown below in Table II. Table II. D22, D21 Control D22 D21 Control Function 0 0 Select Channel 1 0 1 Select Channel 2 1 0 Select Channel 3 1 1 Select Channel 4 D20–D16 : Determines the package address. The five address bits allow up to 32 separate packages to be individually de- coded. Successful decoding is accomplished when these five bits match up with the five hardwired pins on the physical package. D15–D0 : DAC Data to be loaded into identified DAC Input Register. This data must have two leading 0s followed by 14 bits of data, MSB first. The MSB is in location D13 of the 24-bit data stream. Data Loading—AD7835, Parallel Loading Device Data can be loaded into the AD7835 in either straight 14-bit wide words or in two 8-bit bytes. In systems which can transfer 14-bit wide data, the BYSHF input should be hardwired to VCC. This sets up the AD7835 as a straight 14-bit parallel-loading DAC. In 8-bit bus systems where it is required to transfer data in two bytes, it is necessary to have the BYSHF input under logic con- trol. In such a system the top 6 pins of the device data bus, DB8–DB13, must be hardwired to DGND. New low byte data is loaded into the lower 8 places of the selected input register by carrying out a write operation while holding BYSHF high. A second write operation is subsequently executed with BYSHF low and the 6 MSBs on the DB0–DB5 inputs (DB5 = MSB). D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD. CONTROL BIT TO USE/IGNORE FOLLOWING 23 BITS OF INFORMATION CHANNEL ADDRESS MSB, D1 CHANNEL ADDRESS LSB, D2 PACKAGE ADDRESS MSB, PA4 PACKAGE ADDRESS, PA3 PACKAGE ADDRESS, PA2 PACKAGE ADDRESS, PA1 PACKAGE ADDRESS LSB, PA0 LSB, DB0 SECOND LSB, DB1 THIRD LSB, DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 THIRD MSB, DB11 SECOND MSB, DB12 MSB, DB13 SECOND LEADING ZERO FIRST LEADING ZERO Figure 12. Bit Assignments for 24-Bit Data Stream of AD7834 GENERAL DESCRIPTION DAC Architecture—General Each channel consists of a segmented 14-bit R-2R voltage-mode DAC. The full- scale output voltage range is equal to the entire reference span of VREF(+) – VREF(–). The DAC coding is straight binary; all 0s produces an output of VREF(–); all 1s pro- duces an output of VREF(+) – 1 LSB. The analog output voltage of each DAC channel reflects the contents of its own DAC latch. Data is transferred from the ex- ternal bus to the input register of each DAC latch on a per channel basis. The AD7835 has a feature whereby using the A2 pin, data can be transferred from the input data bus to all four input registers simultaneously. Bringing the CLR line low switches all the signal outputs, VOUT1 to VOUT4, to the voltage level on the DSG pin. The sig- nal outputs are held at this level after the removal of the CLR signal and will not switch back to the DAC outputs until the LDAC signal is exercised. Data Loading—AD7834, Serial Input Device A write operation transfers 24 bits of data to the AD7834. The first 8 bits are control data and the remaining 16 bits are DAC data (see Figure 12). The control data identifies the DAC chan- nel to be updated with new data and which of 32 possible pack- ages the DAC resides in. In any communication with the device the first 8 bits must always be control data. Note that the DAC output voltages, VOUT1 to VOUT4, can be updated to reflect new data in the DAC input registers in one of two ways. The first method normally keeps LDAC high and only pulses LDAC low momentarily to update all DAC latches simultaneously with the contents of their respective input regis- ters. The second method ties LDAC low, and channel updating occurs on a per channel basis after new data has been clocked into the AD7834. With LDAC low, the rising edge of FSYNC transfers the new data directly into the DAC latch, updating the analog output voltage. Data being shifted into the AD7834 enters a 24-bit long shift register. If more than 24 bits are clocked in before FSYNC goes high, the last 24 bits transmitted are used as the control data and DAC data. Individual bit functions are discussed below. D23 : Determines whether the following 23-bits of address and data should be used or should be ignored. This is effectively a software Chip Select bit. D23 is the first bit to be transmitted in the 24-bit long word. |
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同様の説明 - AD7834AR |
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