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AD7856AN データシート(PDF) 4 Page - Analog Devices

部品番号 AD7856AN
部品情報  5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC
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ホームページ  http://www.analog.com
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AD7856AN データシート(HTML) 4 Page - Analog Devices

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AD7856
–4–
REV. A
TIMING SPECIFICATIONS1 (V
DD = 5 V; TA = TMIN to TMAX, unless otherwise noted. A Grade: fCLKIN = 6 MHz; K Grade: fCLKIN = 4 MHz.)
Limit at TMIN, TMAX
Parameter
A Version
K Version
Units
Description
fCLKIN
2
500
500
kHz min
Master Clock Frequency
6
4
MHz max
fSCLK
6
4
MHz max
t1
3
100
100
ns min
CONVST Pulsewidth
t2
50
50
ns max
CONVST
↓ to BUSY↑ Propagation Delay
tCONVERT
3.5
5.25
µs max
Conversion Time = 20 tCLKIN
t3
–0.4 tSCLK
–0.4 tSCLK
ns min
SYNC
↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
±0.4 t
SCLK
±0.4 t
SCLK
ns min/max
SYNC
↓ to SCLK↓ Setup Time (Continuous SCLK Input)
t4
4
30
50
ns max
Delay from
SYNC
↓ Until DOUT 3-State Disabled
t5
4
30
50
ns max
Delay from
SYNC
↓ Until DIN 3-State Disabled
t6
4
45
75
ns max
Data Access Time After SCLK
t7
30
40
ns min
Data Setup Time Prior to SCLK
t8
20
20
ns min
Data Valid to SCLK Hold Time
t9
0.4 tSCLK
0.4 tSCLK
ns min
SCLK High Pulsewidth
t10
0.4 tSCLK
0.4 tSCLK
ns min
SCLK Low Pulsewidth
t11
30
30
ns min
SCLK
↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 tSCLK
30/0.4 tSCLK
ns min/max
(Continuous SCLK)
t12
5
50
50
ns max
Delay from
SYNC
↑ Until DOUT 3-State Enabled
t13
90
90
ns max
Delay from
SCLK
↑ to DIN Being Configured as Output
t14
6
50
50
ns max
Delay from
SCLK
↑ to DIN Being Configured as Input
t15
2.5 tCLKIN
2.5 tCLKIN
ns max
CAL
↑ to BUSY↑ Delay
t16
2.5 tCLKIN
2.5 tCLKIN
ns max
CONVST
↓ to BUSY↑ Delay in Calibration Sequence
tCAL
41.7
62.5
ms typ
Full Self-Calibration Time, Master Clock Dependent
(250026 tCLKIN)
tCAL1
37.04
55.5
ms typ
Internal DAC Plus System Full-Scale Cal Time, Master
Clock Dependent (222228 tCLKIN)
tCAL2
4.63
6.94
ms typ
System Offset Calibration Time, Master Clock Dependent
(27798 tCLKIN)
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V.
See Table X and timing diagrams for different interface modes and calibration.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3The
CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5t
12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6t
14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 14, quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
Specifications subject to change without notice.


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