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AD7856AN データシート(PDF) 7 Page - Analog Devices

部品番号 AD7856AN
部品情報  5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC
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ホームページ  http://www.analog.com
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AD7856AN データシート(HTML) 7 Page - Analog Devices

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AD7856
–7–
REV. A
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
1
CONVST
Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode
and starts conversion. When this input is not used, it should be tied to DVDD.
2
BUSY
Busy Output. The busy output is triggered high by the falling edge of
CONVST or rising edge of CAL,
and remains high until conversion is completed. BUSY is also used to indicate when the AD7856 has
completed its on-chip calibration sequence.
3
SLEEP
Sleep Input/Low Power Mode. A Logic 0 initiates a sleep, and all circuitry is powered down, including
the internal voltage reference, provided there is no conversion or calibration being performed. Calibration
data is retained. A Logic 1 results in normal operation. See Power-Down section for more details.
4
REFIN/REFOUT
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is
the reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and
this appears at the pin. This pin can be overdriven by an external reference or can be taken as high as
AVDD. When this pin is tied to AVDD, or when an externally applied reference approaches AVDD, the
CREF1 pin should also be tied to AVDD.
5AVDD
Analog Positive Supply Voltage, +5.0 V
± 5%.
6
AGND
Analog Ground. Ground reference for track/hold, reference and DAC.
7CREF1
Reference Capacitor (0.1
µF Multilayer Ceramic in parallel with a 470 nF NPO type). This external
capacitor is used as a charge source for the internal DAC. The capacitor should be tied between the pin
and AGND.
8CREF2
Reference Capacitor (0.01
µF Multilayer Ceramic). This external capacitor is used in conjunction with
the on-chip reference. The capacitor should be tied between the pin and AGND.
9–16
AIN1–AIN8
Analog Inputs. Eight analog inputs that can be used as eight single-ended inputs (referenced to AGND)
or four pseudo-differential inputs. Channel configuration is selected by writing to the control register.
Both the positive and negative inputs cannot go below AGND or above AVDD at any time. Also the posi-
tive input cannot go below the negative input. See Table III for channel selection.
17
CAL
Calibration Input. This pin has an internal pull-up current source of 0.15
µA. A falling edge on this pin
resets all calibration control logic and initiates a calibration on its rising edge. There is the option of
connecting a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on
power-up. This input overrides all other internal operations. If the autocalibration is not required, this
pin should be tied to a logic high.
18
DVDD
Digital Supply Voltage, +5.0 V
± 5%.
19
DGND
Digital Ground. Ground reference point for digital circuitry.
20
DOUT
Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
21
DIN
Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can
act as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).
22
CLKIN
Master clock signal for the device (A Grade: 6 MHz; K Grade: 4 MHz). Sets the conversion and calibra-
tion times.
23
SCLK
Serial Port Clock. Logic Input. The user must provide a serial clock on this input.
24
SYNC
Frame Sync. Logic Input. This pin is level triggered active low and frames the serial clock for the read
and write operations (see Table IX).


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