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AD7856AR データシート(PDF) 3 Page - Analog Devices

部品番号 AD7856AR
部品情報  5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD7856AR データシート(HTML) 3 Page - Analog Devices

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–3–
REV. A
AD7856
Parameter
A Version
1
K Version
1
Units
Test Conditions/Comments
POWER PERFORMANCE
AVDD, DVDD
+4.75/+5.25
+4.75/+5.25
V min/max
IDD
Normal Mode
5
17
17
mA max
AVDD = DVDD = 4.75 V to 5.25 V. Typically 12 mA
Sleep Mode
6
With External Clock On
30
10
µA typ
Full Power-Down. Power Management Bits in Con-
trol Register Set as PMGT1 = 1, PMGT0 = 0
400
500
µA typ
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
With External Clock Off
5
5
µA max
Typically 0.5
µA. Full Power-Down. Power Manage-
ment. Bits in Control Register Set as PMGT1 = 1,
PMGT0 = 0
200
200
µA typ
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
Normal Mode Power Dissipation
89.25
89.25
mW max
VDD = 5.25 V. Typically 60 mW; SLEEP = VDD
Sleep Mode Power Dissipation
With External Clock On
52.5
52.5
µW typ
VDD = 5.25 V. SLEEP = 0 V
With External Clock Off
26.25
26.25
µW max
VDD = 5.25 V. Typically 5.25 µW; SLEEP = 0 V
SYSTEM CALIBRATION
Offset Calibration Span
7
+0.0375
× V
REF/–0.0375 × VREF
V max/min
Allowable Offset Voltage Span for Calibration
Gain Calibration Span
7
+1.01875
× V
REF/–0.98125 × VREF
V max/min
Allowable Full-Scale Voltage Span for Calibration
NOTES
1Temperature ranges as follows: A Version: –40
°C to +105°C. K Version: 0°C to +105°C.
2Specifications apply after calibration.
3SNR calculation includes distortion and noise components.
4Sample tested @ +25
°C to ensure compliance.
5All digital inputs @ DGND except for
CONVST, SLEEP, CAL and SYNC @ DV
DD. No load on the digital outputs. Analog inputs @ AGND.
6CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST, SLEEP, CAL, and SYNC @ DV
DD. No load on the digital outputs.
Analog inputs @ AGND.
7The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7856 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±0.0375 × V
REF, and
the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V REF ± 0.01875 × VREF).
This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.


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