データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD7890BN-2 データシート(PDF) 5 Page - Analog Devices

部品番号 AD7890BN-2
部品情報  LC2MOS 8-Channel, 12-Bit Serial, Data Acquisition System
Download  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD7890BN-2 データシート(HTML) 5 Page - Analog Devices

  AD7890BN-2 Datasheet HTML 1Page - Analog Devices AD7890BN-2 Datasheet HTML 2Page - Analog Devices AD7890BN-2 Datasheet HTML 3Page - Analog Devices AD7890BN-2 Datasheet HTML 4Page - Analog Devices AD7890BN-2 Datasheet HTML 5Page - Analog Devices AD7890BN-2 Datasheet HTML 6Page - Analog Devices AD7890BN-2 Datasheet HTML 7Page - Analog Devices AD7890BN-2 Datasheet HTML 8Page - Analog Devices AD7890BN-2 Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 20 page
background image
AD7890
–5–
REV. A
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
AGND
Analog Ground. Ground reference for track/hold, comparator and DAC.
2
SMODE
Control Input. Determines whether the part operates in its External Clocking (slave) or Self-Clocking
(master) serial mode. With SMODE at a logic low, the part is in its Self-Clocking serial mode with
RFS
and SCLK as outputs. This Self-Clocking mode is useful for connection to shift registers or to
serial ports of DSP processors. With SMODE at a logic high, the part is in its External Clocking
serial mode with SCLK and RFS as inputs. This External Clocking mode is useful for connection to
the serial port of microcontrollers such as the 8XC51 and the 68HCXX and for connection to the
serial ports of DSP processors.
3
DGND
Digital Ground. Ground reference for digital circuitry.
4CEXT
External Capacitor. An external capacitor is connected to this pin to determine the length of the
internal pulse (see CONVST input and Control Register section). Larger capacitances on this pin
extend the pulse to allow for settling time delays through an external antialiasing filter or signal
conditioning circuitry.
5
CONVST
Convert Start. Edge-triggered logic input. A low to high transition on this input puts the track/hold
into hold and initiates conversion provided that the internal pulse has timed out (see Control
Register section). If the internal pulse is active when the CONVST goes high, the track/hold will not
go into hold until the pulse times out. If the internal pulse has timed out when CONVST goes high,
the rising edge of CONVST drives the track/hold into hold and initiates conversion.
6
CLK IN
Clock Input. An external TTL-compatible clock is applied to this input pin to provide the clock
source for the conversion sequence. In the Self-Clocking serial mode, the SCLK output is derived
from this CLK IN pin.
7
SCLK
Serial Clock Input. In the External Clocking (slave) mode (see Serial Interface section) this is an
externally applied serial clock which is used to load serial data to the control register and to access
data from the output register. In the Self-Clocking (master) mode, the internal serial clock, which is
derived from the clock input (CLK IN), appears on this pin. Once again, it is used to load serial data
to the control register and to access data from the output register.
8
TFS
Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the
falling edge of this signal.
9
RFS
Receive Frame Synchronization Pulse. In the External Clocking mode, this pin is an active low logic
input with RFS provided externally as a strobe or framing pulse to access serial data from the output
register. In the Self-Clocking mode, it is an active low output which is internally generated and
provides a strobe or framing pulse for serial data from the output register. For applications which
require that data be transmitted and received at the same time, RFS and TFS should be connected
together.
10
DATA OUT
Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three
address bits of the Control register and the 12 bits of conversion data. Serial data is valid on the
falling edge of SCLK for sixteen edges after RFS goes low. Output coding from the ADC is 2s
complement for the AD7890-10 and straight binary for the AD7890-4 and AD7890-2.
11
DATA IN
Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first
five bits of serial data are loaded to the control register on the first five falling edges of SCLK after
TFS
goes low. Serial data on subsequent SCLK edges is ignored while TFS remains low.
12
VDD
Positive supply voltage, +5 V
± 5%.
13
MUX OUT
Multiplexer Output. The output of the multiplexer appears at this pin. The output voltage range
from this output is 0 V to +2.5 V for the nominal analog input range to the selected channel. The
output impedance of this output is nominally 3.5 k
Ω. If no external antialiasing filter is required,
MUX OUT should be connected to SHA IN.
14
SHA IN
Track/Hold Input. The input to the on-chip track/hold is applied to this pin. It is a high impedance
input and the input voltage range is 0 V to +2.5 V.
15
AGND
Analog Ground. Ground reference for track/hold, comparator and DAC.
16
VIN1
Analog Input Channel 1. Single-ended analog input. The analog input range on is
±10 V
(AD7890-10), 0 V to +4.096 V (AD7890-4) and 0 V to +2.5 V (AD7890-2). The channel to be con-
verted is selected using the A0, A1 and A2 bits in the control register. The multiplexer has guaran-
teed break-before-make operation.


同様の部品番号 - AD7890BN-2

メーカー部品番号データシート部品情報
logo
Analog Devices
AD7890BN-2 AD-AD7890BN-2 Datasheet
392Kb / 29P
   8-Channel, 12-Bit Serial Data Acquisition System
More results

同様の説明 - AD7890BN-2

メーカー部品番号データシート部品情報
logo
Analog Devices
AD7890 AD-AD7890_17 Datasheet
392Kb / 29P
   8-Channel, 12-Bit Serial Data Acquisition System
AD7891 AD-AD7891 Datasheet
173Kb / 20P
   LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System
REV. A
AD7891YSZ-2 AD-AD7891YSZ-2 Datasheet
1Mb / 20P
   LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System
REV. D
AD7891AP AD-AD7891AP Datasheet
316Kb / 20P
   LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System
REV. D
AD7891 AD-AD7891_04 Datasheet
1Mb / 20P
   LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System
REV. D
AD7890 AD-AD7890_15 Datasheet
480Kb / 28P
   LC MOS 8-Channel, 12-Bit Serial Data Acquisition System
REV. C
AD7874 AD-AD7874 Datasheet
414Kb / 16P
   LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
REV. C
5962-9152101MXA AD-5962-9152101MXA Datasheet
326Kb / 16P
   LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
REV. C
AD7874SQ AD-AD7874SQ Datasheet
326Kb / 16P
   LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
REV. C
AD7874BNZ AD-AD7874BNZ Datasheet
326Kb / 16P
   LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
REV. C
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com