AD7896

REV. B

–7–

OPERATING MODES

Mode 1 Operation (High Sampling Performance)

The timing diagram in Figure 2 is for optimum performance in

Operating Mode 1 where the falling edge of CONVST starts

conversion and puts the Track/Hold amplifier into its hold

mode. This falling edge of CONVST also causes the BUSY sig-

nal to go high to indicate that a conversion is taking place. The

BUSY signal goes low when the conversion is complete which is

8

µs max after the falling edge of CONVST, and new data from

this conversion is available in the output register of the AD7896.

A read operation accesses this data. This read operation consists

of 16 clock cycles, and the length of this read operation will de-

pend on the serial clock frequency. For the fastest throughput

rate (with a serial clock of 10 MHz 5 V operation) the read op-

eration will take 1.6

µs. The read operation must be complete at

least 400 ns before the falling edge of the next CONVST, and

this gives a total time of 10

µs for the full throughput time

(equivalent to 100 kHz). This mode of operation should be used

for high sampling applications.

14

µs shown in diagram from the rising edge of CONVST. This

is because the Track/Hold amplifier goes into its hold mode on

the falling edge of CONVST and then the conversion will not be

complete for a further 8

µs. In this case the BUSY will be the

best indicator for when the conversion is complete. Even though

the part is in sleep mode, data can still be read from the part.

The read operation consists of 16 clock cycles as in Mode 1 op-

eration. For the fastest serial clock of 10 MHz 5 V operation the

read operation will take 1.6

µs, and this must be complete at

least 400 ns before the falling edge of the next CONVST to al-

low the Track/Hold amplifier to have enough time to settle.

This mode is very useful when the part is converting at a slow

rate as the power consumption will be significantly reduced

from that of Mode 1 operation.

Mode 2 Operation (Auto Sleep After Conversion)

The timing diagram in Figure 3 is for optimum performance in

Operating Mode 2 where the part automatically goes into sleep

mode once BUSY goes low after conversion and “wakes up” be-

fore the next conversion takes place. This is achieved by keeping

CONVST

low at the end of conversion whereas it was high at

the end of conversion for Mode 1 operation. The rising edge of

CONVST

“wakes up” the part. This wake-up time is 6

µs at

which point the Track/Hold amplifier goes into its hold mode.

The conversion takes 8

µs after this, provided the CONVST

has gone low, giving a total of 14

µs from the rising edge of

CONVST

to the conversion being complete which is indicated

by the BUSY going low. Note that since the wake-up time from

the rising edge of CONVST is 6

µs, when the CONVST pulse

width is greater than 6

µs the conversion will take more than the

CONVST

BUSY

SCLK

SERIAL READ

OPERATION

CONVERSION ENDS

8µs LATER

OUTPUT

SERIAL

SHIFT

REGISTER

IS RESET

CONVERSION IS

INITIATED AND

TRACK/HOLD GOES INTO

HOLD

400ns MIN

READ OPERATION

SHOULD END 400ns

PRIOR TO NEXT

FALLING EDGE OF

CONVST

Figure 2. Mode 1 Timing Operation Diagram for High Sampling Performance

CONVST

BUSY

SCLK

SERIAL READ

OPERATION

CONVERSION

ENDS

14µs LATER

READ OPERATION

SHOULD END 400ns

PRIOR TO NEXT

FALLING EDGE OF

CONVST

OUTPUT

SERIAL

SHIFT

REGISTER

IS RESET

PART

WAKES

UP

CONVERSION

IS INITIATED

TRACK/HOLD

GOES INTO

HOLD

WAKE-UP

TIME

t

1

400ns MIN

Figure 3. Mode 2 Timing Diagram Where Automatic Sleep Function Is Initiated