AD827

REV. B

–8–

multipliers connected in series. They could also be placed in

parallel with an increase in bandwidth and a reduction in gain.

from 0 to 3 V dc. Measurements show that this circuit easily

supplies 2 V p-p into a 100

Ω load while operating from ±5 V

supplies. The overall bandwidth of the circuit is approximately

7 MHz with 0.5 dB of peaking.

Each half of the AD827 serves as an I/V converter and converts

the output current of one of the two multipliers in the AD539

into an output voltage. Each of the AD539’s two multipliers

contains two internal 6 k

Ω feedback resistors; one is connected

between the CH1 output and Z1, the other between the CH1

output and W1. Likewise, in the CH2 multiplier, one of the

feedback resistors is connected between CH2 and Z2 and the

other is connected between CH2 and Z2. In Figure 25, Z1 and

W1 are tied together, as are Z2 and W2, providing a 3 k

Ω

feedback resistor for the op amp. The 2 pF capacitors connected

between the AD539’s W1 and CH1 and W2 and CH2 pins are

in parallel with the feedback resistors and thus reduce peaking

in the VCA’s frequency response. Increasing the values of C3

and C4 can further reduce the peaking at the expense of

reduced bandwidth. The 1.25 mA full-scale output current of

the AD539 and the 3 k

Ω feedback resistor set the full-scale

output voltage of each multiplier at 3.25 V p-p.

Current limiting in the AD827 (typically 30 mA) limits the out-

put voltage in this application to about 3 V p-p across a 100

Ω

load. Driving a 50

Ω reverse-terminated load divides this value

by two, limiting the maximum signal delivered to a 50

Ω load to

about 1.5 V p-p, which suffices for video signal levels. The

dynamic range of this circuit is approximately 55 dB and is

primarily limited by feedthrough at low input levels and by the

maximum output voltage at high levels.

Guidelines for Grounding and Bypassing

When designing practical high frequency circuits using the

AD827, some special precautions are in order. Both short

interconnection leads and a large ground plane are needed

whenever possible to provide low resistance, low inductance

circuit paths. One should remember to minimize the effects of

capacitive coupling between circuits. Furthermore, IC sockets

should be avoided. Feedback resistors should be of a low

enough value that the time constant formed with stray circuit

capacitances at the amplifier summing junction will not limit

circuit performance. As a rule of thumb, use feedback resistor

values that are less than 5 k

Ω. If a larger resistor value is

necessary, a small (<10 pF) feedback capacitor in parallel with

the feedback resistor may be used. The use of 0.1

µF ceramic

disc capacitors is recommended for bypassing the op amp’s

power supply leads.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Pin Mini-DIP (N) Package

16-Pin SOIC (R) Package

8-Pin Cerdip (Q) Package

20-Terminal Leadless Ceramic Chip Carrier

(E-20A)