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AD8303AR データシート(PDF) 3 Page - Analog Devices |
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AD8303AR データシート(HTML) 3 Page - Analog Devices |
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3 / 16 page  SPECIFICATIONS +5 V OPERATION Parameter Symbol Condition Min Typ1 Max Units STATIC PERFORMANCE Resolution 2 N 12 Bits Relative Accuracy 2 INL –2 ±1/2 +2 LSB Differential Nonlinearity 2 DNL Monotonic, TA = +25°C –3/4 ±1/4 +3/4 LSB Differential Nonlinearity 2 DNL Monotonic –1 ±1/2 +1 LSB Zero-Scale Error VZSE Data = 000H 1.25 +4.5 mV Full-Scale Voltage 3 VFS Data = FFFH 2.039 2.0475 2.056 Volts Full-Scale Tempco 3, 4 TCVFS 16 ppm/ °C ANALOG OUTPUTS Output Current IOUT Data = 800H, ∆VOUT < 3 mV ±3mA Output Resistance to GND ROUT Data = 000H 30 Ω Capacitive Load 4 CL No Oscillation 500 pF REFERENCE OUTPUT Output Voltage V REF Load > 1 M Ω 1V LOGIC INPUTS Logic Input Low Voltage VIL 0.8 V Logic Input High Voltage VIH 2.4 V Input Leakage Current IIL 10 µA Input Capacitance 4 CIL 10 pF INTERFACE TIMING SPECIFICATIONS 4, 5 Clock Width High t CH 30 ns Clock Width Low t CL 30 ns Load Pulse Width t LDW 30 ns Data Setup t DS 15 ns Data Hold t DH 15 ns Reset Pulse Width tRS 30 ns Load Setup tLD1 15 ns Load Hold tLD2 30 ns Select tCSS 30 ns Deselect tCSH 30 ns AC CHARACTERISTICS 4 Voltage Output Settling Time 6 tS To ±0.1% of Full Scale 4 µs Voltage Output Settling Time 6 tS To ±1 LSB of Final Value5 12 µs Shutdown Recovery Time tSDR To ±0.1% of Full Scale 10 µs Output Slew Rate SR Data = 000H to FFFH to 000H 2V/ µs DAC Glitch Q 15 nV s Digital Feedthrough Q 15 nV s SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE DNL < ± 1 LSB 2.7 3.0 5.5 V Shutdown Supply Current IDD_SD SHDN = 0, No Load, VIL = 0 V, TA = +25°C 0.02 1 µA Positive Supply Current 7 IDD VDD = 5 V, VIL = 0 V, No Load 2.1 3.4 mA Power Dissipation PDISS VDD = 5 V, VIL = 0 V, No Load 10.5 17 mW Power Supply Sensitivity PSS ∆V DD = ± 10% 0.001 0.004 %/% NOTES 1Typical readings represent the average value of room temperature operation. 21 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000 H, 001H) are excluded from the linearity error measurement. 3Includes internal voltage reference error. 4These parameters are guaranteed by design and not subject to production testing. 5All input control signals are specified with t R = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. 7See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels. Specifications subject to change without notice. AD8303 REV. 0 –3– (@ VDD = +5 V 10%, –40 C ≤ T A ≤ +85 C, unless otherwise noted) |
同様の部品番号 - AD8303AR |
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同様の説明 - AD8303AR |
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