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AD8403AR10 データシート(PDF) 5 Page - Analog Devices

部品番号 AD8403AR10
部品情報  1-/2-/4-Channel Digital Potentiometers
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD8403AR10 データシート(HTML) 5 Page - Analog Devices

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All VERSIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
SWITCHING CHARACTERISTICS
2, 3
Input Clock Pulse Width
tCH, tCL
Clock Level High or Low
10
ns
Data Setup Time
tDS
5ns
Data Hold Time
tDH
5ns
CLK to SDO Propagation Delay
4
tPD
RL = 1 k
Ω to +5 V, C
L
≤ 20 pF
1
25
ns
CS
Setup Time
tCSS
10
ns
CS
High Pulse Width
tCSW
10
ns
Reset Pulse Width
tRS
50
ns
CLK Fall to CS Rise Hold Time
tCSH
0ns
CS
Rise to Clock Rise Setup
tCS1
10
ns
NOTES
1Typicals represent average readings at +25
°C and V
DD = +5 V.
2Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
3See timing diagram for location of measured values. All input control voltages are specified with t
R = tF = 1 ns (10% to 90% of V DD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using VDD = +3 V or +5 V. To avoid false clocking a minimum input logic slew rate of 1 V/ µs should be maintained.
4Propagation Delay depends on value of V
DD, RL and CL–see applications text.
Specifications subject to change without notice.
AD8400/AD8402/AD8403–SPECIFICATIONS
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8400/AD8402/AD8403 feature proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
(VDD = +3 V
10% or + 5 V
10%, VA = +VDD, VB = 0 V, –40 C
≤ T
A
≤ +85 C unless
otherwise noted)
DAC REGISTER LOAD
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
VDD
0V
SDI
CLK
CS
VOUT
Figure 1a. Timing Diagram
±1 % ERROR BAND
±1 %
t
CSH
t
CSS
t
DH
Ax OR Dx
Ax OR Dx
t
PD_MIN
t
PD_MAX
A'x OR D'x
A'x OR D'x
1
0
1
0
1
0
VDD
0V
SDI
(DATA IN)
CLK
CS
VOUT
1
0
SDO
(DATA OUT)
t
DS
t
CH
t
CS1
t
CL
t
S
t
CSW
Figure 1b. Detail Timing Diagram
±1%
±1% ERROR BAND
RS
1
0
VDD
VDD/2
VOUT
t
RS
t
S
Figure 1c. Reset Timing Diagram
–5–
REV. B
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
AX–BX, AX–WX, BX–WX . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40
°C to +85°C
Maximum Junction Temperature (TJ max) . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300
°C
Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA
Thermal Resistance
JA)
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +83
°C/W
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +63
°C/W
SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . +70
°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . +120
°C/W
TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . +180
°C/W
TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . +143
°C/W
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.


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